名称:Quartus洗衣机控制器Verilog代码远程云端平台(文末获取)
软件:Quartus
语言:Verilog
代码功能:
洗衣机控制器设计要求
设计一个电子定时器,控制洗衣机作如下运转定时启动→正转20秒→暂停10秒→反转20秒→暂停10秒,每个循环1分钟;
按正计时方式用两个数码管显示正转、暂停、反
转时间,同时用三只LED灯表示“正转”
反转”、“暂停”三个状态;
用两个数码管显示洗涤的预置时间(分钟数),按倒计时方式对洗涤过程作计时显示,时间到停机,停机指示灯亮
洗涤过程由“开始”开关开始,设置“暂停”开关。
本代码已在远程云端平台验证,远程云端平台如下,其他远程云端平台可以修改管脚适配:
部分代码展示:
module washing_machine(clk_in, dataout,en,reset_n, start_key, stop_key,led, end_beep); input clk_in;//1000Hz input reset_n;//复位按下低电平 input start_key;//启动按下低电平 input stop_key;//暂停按下低电平 output [2:0] led;//正反转灯 output end_beep;//结束报警 output[7:0] dataout;//数码管段选 output[3:0] en;//COM使能输出 reg [1:0] state; reg [2:0] led; reg [7:0] washing_time; reg end_beep_buf; reg [7:0] second_cnt; reg min_en; reg second_en_1s; reg [31:0] second_div_cnt; reg [31:0] beep_cnt=32'd0; always @(posedge clk_in or negedge reset_n) if(!reset_n) state<=2'b00;//空闲状态 else case (state) 2'b00 ://空闲状态 if (start_key == 1'b0) state <= 2'b01; else state <= 2'b00; 2'b01 ://倒计时状态 if(stop_key==0) state <= 2'b11; else if (washing_time > 8'b00000000) state <= 2'b01; else state <= 2'b10; 2'b10 ://结束 state <= 2'b10; 2'b11 ://暂停 if (start_key == 1'b0) state <= 2'b01; else state <= 2'b11; default : state <= 2'b00; endcase always @(posedge clk_in) begin if (state == 2'b10)//结束计数 beep_cnt <=beep_cnt+ 1'b1; end always @(posedge clk_in) begin if (state == 2'b10)//结束 end_beep_buf <= 1'b1; else end_beep_buf <= 1'b0; end assign end_beep = end_beep_buf; always @(posedge clk_in) if(state!=2'b01)//非倒计时状态清零 begin second_div_cnt <= 32'd0; second_en_1s <= 1'b0; end else//倒计时状态计时 begin if (second_div_cnt >= 32'd1000)//计数1000为1s,仿真将计数器改小为50 begin second_div_cnt <= 32'd0; second_en_1s <= 1'b1;//50MHz分频为1Hz end else begin second_div_cnt <= second_div_cnt + 32'd1; second_en_1s <= 1'b0; end end always @(posedge clk_in) begin if (state!=2'b01)//非倒计时状态清零 second_cnt <= 8'b00000000; else if (second_en_1s == 1'b1)//倒计时状态计时 begin if (second_cnt >= 8'd59)//59s second_cnt <= 8'd0; else second_cnt <= second_cnt + 8'd1; end else second_cnt <= second_cnt; end always @(posedge clk_in) begin if (second_en_1s == 1'b1 && second_cnt == 8'd59) min_en <= 1'b1;//分钟信号 else min_en <= 1'b0; end always @(posedge clk_in) begin if (state == 2'b00) washing_time <= 8'd5;//默认5分钟 else if (min_en == 1'b1)//分钟信号 begin if (washing_time > 8'd0) washing_time <= washing_time - 8'd1;//倒计时 else washing_time <= 8'd0; end else washing_time <= washing_time; end reg [7:0] second_time; always @(posedge clk_in) if(state==2'b01) begin if (washing_time > 8'b00000000) begin if (second_cnt < 8'd20)//秒计时小于20,正转灯亮 led <= 3'b100; else if (second_cnt >= 8'd20 & second_cnt < 8'd30)//秒计时20~30,暂停灯亮 led <= 3'b010; else if (second_cnt >= 8'd30 & second_cnt < 8'd50)//秒计时30~50,反转灯亮 led <= 3'b001; else led <= 3'b010;//秒计时50~59,暂停灯亮 end else led <= 3'b000; end else led <= 3'b000; always @(posedge clk_in) if(state==2'b01) begin if (washing_time > 8'b00000000) begin if (second_cnt < 8'd20)//秒计时小于20,正转灯亮 second_time <= second_cnt; else if (second_cnt >= 8'd20 & second_cnt < 8'd30)//秒计时20~30,暂停灯亮 second_time <= second_cnt-20; else if (second_cnt >= 8'd30 & second_cnt < 8'd50)//秒计时30~50,反转灯亮 second_time <= second_cnt-30; else second_time <= second_cnt-50;//秒计时50~59,暂停灯亮 end else second_time <= 8'b0; end else second_time <= 8'b0; //实现的动态数码管显示 reg[7:0] dataout;//各段数据输出 reg[3:0] en; reg [7:0] data_num; //数码管位选 reg [1:0]sel_cnt =2'd0; always @(posedge clk_in ) //4个数码管 begin sel_cnt<=sel_cnt+2'd1; end always @(*) //位选切换 begin case (sel_cnt) 2'd0: begin en<=~4'b0111; data_num<= second_time%10; end 2'd1: begin en<=~4'b1011; data_num <= second_time/10; end 2'd2: begin en<=~4'b1101; data_num <= washing_time%10; end 2'd3: begin en<=~4'b1110; data_num <= washing_time/10; end default:; endcase end always @(*) begin case (data_num) //数字显示码 8'd0: dataout<= 8'b1100_0000; 8'd1: dataout<= 8'b1111_1001; 8'd2: dataout<= 8'b1010_0100; 8'd3: dataout<= 8'b1011_0000; 8'd4: dataout<= 8'b1001_1001; 8'd5: dataout<= 8'b1001_0010; 8'd6: dataout<= 8'b1000_0010; 8'd7: dataout<= 8'b1111_1000; 8'd8: dataout<= 8'b1000_0000; 8'd9: dataout<= 8'b1001_0000; default:; endcase end endmodule
源代码
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