verilog 输入4个4位的二进制数，从小到大排序后

eachanm

已于 2023-04-12 22:16:11 修改

阅读量998

点赞数 1

分类专栏： FPGA 文章标签： fpga开发 verilog Powered by 金山文档

于 2023-02-24 20:41:54 首次发布

本文链接：https://blog.csdn.net/eachanm/article/details/129208042

版权

FPGA 专栏收录该内容

18 篇文章 23 订阅

订阅专栏

文章描述了两个Verilog模块，用于对输入数据进行排序。第一个模块使用并行输入并立即输出排序结果，而第二个模块则在每个时钟周期接收一个串行输入位，逐步完成整个序列的排序。排序过程通过自定义的任务函数实现。

摘要由CSDN通过智能技术生成

主要学习任务的使用

module mux2_1
(
    input   wire        sys_clk,
    input   wire        sys_rst_n,
    input   wire [3:0]  a, b, c, d,
    
    output reg [3:0]    ra, rb, rc, rd
);

reg [3:0] va, vb, vc, vd;

always@ (a or b or c or d)
    begin
        {va, vb, vc, vd} = {a, b, c, d};
        sort(va, vc);       //va和vc比较大小并互换
        sort(vb, vd); 
        sort(va, vb); 
        sort(vc, vd); 
        sort(vb, vc); 
        {ra, rb, rc, rd} = {va, vb, vc, vd};
    end


task sort;
    inout [3:0] x, y;
    reg [3:0] tmp;
    if(x > y)
        begin
            tmp = x;
            x = y;
            y = tmp;
        end
endtask



endmodule

仿真文件

`timescale  1ns/1ns
module tb_mux2_1();
reg sys_clk;
reg sys_rst_n;
reg [3:0] a, b, c, d;
wire [3:0] ra, rb, rc, rd;



initial
    begin
        sys_clk <= 1'b0;
        sys_rst_n <= 1'b0;
        #20
        sys_rst_n <= 1'b1;
    end

always #10 sys_clk <= ~sys_clk;

always @(posedge sys_clk)
    begin
        a <= {$random} % 15;
        b <= {$random} % 15;
        c <= {$random} % 15;
        d <= {$random} % 15;
    end
    
mux2_1 mux2_1_inst
(
    .sys_clk         (sys_clk),
    .sys_rst_n       (sys_rst_n),
    .a               (a),
    .b               (b),   
    .c               (c),
    .d               (d),        
                    
    .ra               (ra),
    .rb               (rb),   
    .rc               (rc),
    .rd               (rd) 
);

endmodule

2、按照时钟节拍串行输入的,要求用时钟触发任务的执行法,每个时钟周期完成一次数据


module mux2_1
(
    input   wire        sys_clk,
    input   wire        sys_rst_n,
    input   wire [7:0]  num,      //串行输入4个数据
    
    output reg [7:0]    ra, rb, rc, rd  //输出排序好的数
);

reg [7:0] va, vb, vc, vd;
reg [7:0] ta, tb, tc, td;
reg [3:0] state;

parameter IN0 = 4'b0001,
          IN1 = 4'b0010,
          IN2 = 4'b0011,
          IN3 = 4'b0100,
          T1 = 4'b0101,
          T2 = 4'b0110,
          T3 = 4'b0111,
          T4 = 4'b1000,
          T5 = 4'b1001;
          

always@ (posedge sys_clk or negedge sys_rst_n)
    if(sys_rst_n == 1'b0)
        state <= IN0;
    else
        case (state) 
            IN0: begin
                va <= num;
                state <= IN1;
            end
            IN1: begin
                vb <= num;
                state <= IN2;
            end
            IN2: begin 
                vc <= num;
                state <= IN3;
            end
            IN3: begin
                vd <= num;
                state <= T1;
                {ta, tb, tc, td} <= {va, vb, vc, vd};
            end
            T1: begin
                sort(va, vc);
                state <= T2;
            end
            T2: begin
                sort(vb, vd);
                state <= T3;
            end
            T3: begin
                sort(va, vb);
                state <= T4;
            end
            T4: begin
                sort(vc, vd);
                state <= T5;
            end
            T5: begin
                sort(tb, tc);
                {ra, rb, rc, rd} <= {va, vb, vc, vd};
                state <= IN0;
            end
            default:
                state <= IN0;
        endcase


task sort;
    inout [7:0] x, y;
    reg [7:0] tmp;
    if(x > y)
        begin
            tmp = x;
            x = y;
            y = tmp;
        end
endtask



endmodule