特权同学《Verilog边码边学》P15 11 频率计数器 作业答案 设计高频脉冲计数器

题目

 程序

design

`timescale 1ns/1ps
module vlg_design(
	input i_clk,
	input i_rst_n,
	input i_pulse,
	input i_en,
	output o_vld,
	output[15:0] o_pulse_cnt   //频率计数

    );

reg[1:0] r_pulse;
wire w_rise_edge;   //脉冲上升沿检测信号	
wire w_fall_edge;   //脉冲下降沿检测信号

///
//输出信号产生

assign o_vld = 	w_fall_edge;   


//脉冲边沿检测逻辑	

always @(posedge i_clk)	
	if(!i_rst_n) r_pulse <= 2'b00;
	else r_pulse <= {r_pulse[0],i_pulse};

assign w_rise_edge = r_pulse[0] & ~r_pulse[1];
assign w_fall_edge = ~r_pulse[0] & r_pulse[1];

///
//脉冲计数逻辑
reg[15:0] r_pulse_cnt;

always @(posedge i_clk)	
	if(i_en) begin
		if(w_rise_edge) r_pulse_cnt <= 'b0; //因为这里清零(初始值取0)了，所以最后要加上1
		else begin
			if(w_fall_edge) r_pulse_cnt <= 'b0; 
			else r_pulse_cnt <= r_pulse_cnt + 1;
		end	
	end		
	else ;
	
/* always @(posedge i_clk)	
	if(!i_en) r_pulse_cnt <= 'b0;
	else if(w_rise_edge) r_pulse_cnt <= 'b0;   //因为这里清零了，所以最后要加上1
	else if(w_fall_edge) r_pulse_cnt <= 'b0;
	else r_pulse_cnt <= r_pulse_cnt + 1;	 */


assign o_pulse_cnt = r_pulse_cnt + 1'b1;

endmodule

testbench

`timescale 1ns/1ps
module testbench_top();
	

//参数定义

`define CLK_PERIORD		10		//时钟周期设置为10ns（100MHz）	


//接口申明
	
reg clk;
reg rst_n;
reg i_pulse;
reg i_en;
wire[15:0] o_pulse_cnt;
wire o_vld; 

	
//对被测试的设计进行例化
	
vlg_design		uut_vlg_design(
	.i_clk(clk),
	.i_rst_n(rst_n),
	.i_pulse(i_pulse),
	.i_en(i_en),
	.o_pulse_cnt(o_pulse_cnt),
	.o_vld(o_vld)
    );	
	

//复位和时钟产生

	//时钟和复位初始化、复位产生
initial begin
	clk <= 0;
	rst_n <= 0;
	#1000;
	rst_n <= 1;
end
	
	//时钟产生
always #(`CLK_PERIORD/2) clk = ~clk;	


//测试激励产生
integer i;

initial begin

	i_pulse <= 1'b0;
	i_en <= 1'b0;
	@(posedge rst_n);	//等待复位完成
	
	@(posedge clk);
	
	repeat(10) begin
		@(posedge clk);
	end
	#4;
	//i_pulse <= 1'b1;
	
	i_en <= 1'b1;
	for(i=0; i<50; i=i+1) begin
		#1000;
		i_pulse <= 1'b1;
		#1000;   //高脉冲持续时间为1000ns，计数应为100
		i_pulse <= 1'b0;
	end	
	i_en <= 1'b0;
	#10_000;
	
	i_en <= 1'b1;
	for(i=0; i<69; i=i+1) begin
		#5000;
		i_pulse <= 1'b1;
		#5000;//高脉冲持续时间为5000ns，计数应为500
		i_pulse <= 1'b0;
	end	
	i_en <= 1'b0;
	#10_000;
	
	i_en <= 1'b0;   //使能为0了，计数不用管了
	for(i=0; i<15; i=i+1) begin
		#5000;
		i_pulse <= 1'b1;
		#5000;
		i_pulse <= 1'b0;
	end	
	i_en <= 1'b0;
	#10_000;

	repeat(10) begin
		@(posedge clk);
	end	
	#4;
	i_pulse <= 1'b0;
	
	repeat(10) begin
		@(posedge clk);
	end
	
	$stop;
end


endmodule