《从0开始设计和实现CPU》总线设计（三）之地址解码器的实现

功能：地址解码器的实现

1.总线框图

2.程序源码

  /****功能：地址解码器的实现****/ 
`include "stddef.h"
`include "global_config.h"

`include "bus.h"

module bus_addr_dec(

     /****总线从属共享信号****/
	  input wire [`WordAddrBus]  s_addr,    //地址 29：0
	  /****总线从属0~7号****/
	  output reg                  s0_cs_,    //片选
      output reg                  s1_cs_,    //片选
      output reg                  s2_cs_,    //片选
	  output reg                  s3_cs_,    //片选
	  output reg                  s4_cs_,    //片选
	  output reg                  s5_cs_,    //片选
	  output reg                  s6_cs_,    //片选
	  output reg                  s7_cs_     //片选

) ;

	 /****生成总线从属索引****/
	 // wire[2:0]     s_index =  s_addr[29:27];  数字采用宏定义
	 wire[`BusSlaveLndexBus]   s_index =  s_addr[`BusSlaveLndexLoc];
	 
	 always @(*)begin
	     //初始化片选信号
	    s0_cs_ = `DISABLE_;
		s1_cs_ = `DISABLE_;
		s2_cs_ = `DISABLE_;
		s3_cs_ = `DISABLE_;
		s4_cs_ = `DISABLE_;
		s5_cs_ = `DISABLE_;
		s6_cs_ = `DISABLE_;
	    s7_cs_ = `DISABLE_;	
	 //根据地址信号片选出总线从属进行访问！
	   case(s_index)
		    `BUS_SLAVE_0:begin    
			  s0_cs_ = `ENABLE_;
			  end
			  
			 `BUS_SLAVE_1:begin
			  s1_cs_ = `ENABLE_;
			  end
			  
			 `BUS_SLAVE_2:begin
			  s2_cs_ = `ENABLE_;
			  end
			  
			 `BUS_SLAVE_3:begin
			  s3_cs_ = `ENABLE_;
			  end
			  
			 `BUS_SLAVE_4:begin
			  s4_cs_ = `ENABLE_;
			  end
			  
			 `BUS_SLAVE_5:begin
			  s5_cs_ = `ENABLE_;
			  end
			  
			 `BUS_SLAVE_6:begin
			  s6_cs_ = `ENABLE_;
			  end
			  
			 `BUS_SLAVE_7:begin
			  s7_cs_ = `ENABLE_;
			  end
			   
		endcase
	 end
endmodule