cuda cache相关知识总结

cache line 疑惑

问

I was reading about the L1 and L2 caches load and store and I have found that if there is a miss in L1 for a load instruction, L1 will get only the sector (32byte) of the 128 cache line from L2. But why do we say that the granularity of a fetching is 128byte? In which case do we fetch 128bytes? and what is the advantage of getting only 1 sector in a cache miss?

答

In Fermi/Kepler days, a miss on the L1 triggered a 128byte request to the L2. Somewhere between Maxwell and Pascal this changed to a 32-byte granularity. You’ll fetch 128 bytes if you have a request that needs 128 bytes. For example if you have a warp-wide load of a float or int per thread, adjacent. The advantage of getting only 1 sector on a cache miss needs to be considered in the case of a warp request that only needs 32 bytes or less. In that case, it is preferable to request 32 bytes rather than 128.