《Digital Integrated Circuit》读后笔记 (三)

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chapter six Static CMOS Design

1. combinational logic

sequential logic a combinational logic portion and a module that holds the state

2. Static CMOS Design

static complementary CMOS output is either $V_{DD}$ or $V_{SS}$ through a low-resistance path.

dynamic circuit class relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes. simpler and faster sensitive to noise

• complementary CMOS
• ratioed logic(pseudo-NMOS and DCVSL)
• pass-transistor logic

3. Complementary CMOS

pull-up network PUN PMOS

pull-down network PDN NMOS

series devices and parallel devices duality principle

N-input logic gate is 2N

sub-nets(SN)

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Static properties: (Noise Margin)

• A=B=0->1: a strong pull-up
• A=1, B=0->1: $V_{Tn1}=V_{tn0}$
• A=0->1, B=0: $V_{Tn2}=V_{tn0}+\gamma ((\sqrt{|2{\varphi }_T+V_{int}|}-\sqrt{2{\varphi }_T}))$

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Propagation Delay:

depends upon the input patterns

$t_{pLH}=0.69R_p{C}_L$

$t_{pHL}=0.69(2R_N{C}_L)$

To make the same delay, NMOS devices must be made twice as wide. PMOS remain unchanged.

High-to-low propagation delay depends on the state of the internal nodes.

PMOS devices have a lower mobility relative to NMOS devices, stacking devices in series must be avoided as much as possible.

NAND is better than NOR.

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$$t_{pHL}=0.69(R_1{C}_1+(R_1+R_2)C_2+(R_1+R_2+R_3)C_3$$