中国工业行业分类英文翻译

 摘自Online Appendix for Exports and Credit Constraints under Incomplete Information: Theory and Evidence from China

http://mjyu.ccer.edu.cn/RESTAT_appendix.pdf





Table Al: Total Factor Productivity of Chinese  Plants (2000-2008)

 

Adjusted Chinese Industrial Classfication

Labor

Capital

Mean

Variance

(2-digit)

coeff.

coeff.

TFP1     TFP2

TFP1     TFP2

Processing of Foods (13)

0.438

0.467

3.215

3.370

1.496

1.288

Manufacturing of Foods (14)

0.438

0.388

3.585

3.467

1.308

2.205

Manufacture of Beverages (15)

0.466

0.509

2.460

2.276

1.381

1.639

Manufacture of Tobacco (16)

0.441

0.668

0.645

2.080

1.241

4.768

Manufacture of Textile (17)

0.433

0.290

4.328

4.487

1.084

0.567

Manufacture of Apparel, Footwear & Caps (18)

0.498

0.355

3.408

3.275

1.023

0.379

Manufacture of Leather, Fur, & Feather (19)

0.475

0.421

3.160

3.346

1.191

0.567

Processing  of Timber,  Manufacture of Wood,

0.436

0.546

2.598

2.518

1.323

2.019

Bamboo, Rattan, Palm & Straw Products (20)

 

 

 

 

 

 

Manufacture of Furniture (21)

0.559

0.375

3.147

2.958

1.225

0.773

Manufacture of Paper & Paper Products (22)

0.472

0.359

3.564

3.417

1.167

0.525

Printing, Reproduction of Recording Media (23)

0.417

0.340

3.869

3.615

1.033

0.708

Manufacture of Articles For Culture, Education

0.493

0.245

4.257

4.366

0.963

0.727

& Sport Activities (24)

 

 

 

 

 

 

Processing of Petroleum, Coking, &Fuel (25)

0.234

0.568

2.901

3.150

1.593

3.301

Manufacture of Raw Chemical Materials (26)

0.307

0.446

3.823

3.675

1.258

1.019

Manufacture of Medicines (27)

0.414

0.333

4.291

4.556

1.249

0.467

Manufacture of Chemical Fibers (28)

0.383

0.488

2.998

3.563

1.437

1.848

Manufacture of Rubber (29)

0.377

0.368

3.995

3.798

1.106

1.227

Manufacture of Plastics (30)

0.414

0.478

2.993

2.819

1.218

1.445

Manufacture of Non-metallic Mineral goods (31)

0.311

0.468

3.521

3.577

1.260

1.498

Smelting & Pressing of Ferrous Metals (32)

0.452

0.453

3.214

3.371

1.544

1.599

Smelting & Pressing of Non-ferrous Metals (33)

0.367

0.332

4.400

4.834

1.299

0.806

Manufacture of Metal Products (34)

0.413

0.389

3.774

3.865

1.228

0.916

Manufacture of General Purpose Machinery (35)

0.401

0.387

3.849

3.573

1.158

0.860

Manufacture of Special Purpose Machinery (36)

0.402

0.421

3.575

3.462

1.181

1.217

Manufacture of Transport Equipment (37)

0.460

0.447

3.107

3.000

1.237

0.840

Electrical Machinery & Equipment (39)

0.451

0.403

3.723

3.301

1.209

0.671

Computers & Other Electronic Equipment (40)

0.491

0.263

4.526

4.812

1.258

1.110

Manufacture of Measuring Instruments &  Ma-

0.407

0.450

3.451

3.665

1.332

2.061

chinery for Cultural Activity & Offce Work (41)

 

 

 

 

 

 

Manufacture of Artwork  (42)

0.462

0.398

3.364

3.793

1.180

1.005

 

Notes   We  do not report standard errors  for each coeffcient to  save space though  available upon request. The logarithm  of  firm  productivity  for  Chinese non-SOEs  firms (TFP1  and TFP2)  is  estimated  by industry by the augmented Olley-Pakes approach introduced in the text.   Coeffcients of labor and capital  are  calculated at  the sectoral average whereas TFP1 and TFP2 is measured at firm-levelusing firm-levelvalue-added, capital,and labor,respectively. The last four columns report the sectoral mean and variance of log TFP1 and TFP2, respectively.

 

 

 

 

 

 

 

 

 

 

 

13

在电子设计自动化(EDA)领域,Verilog HDL 是一种重要的硬件描述语言,广泛应用于数字系统的设计,尤其是在嵌入式系统、FPGA 设计以及数字电路教学中。本文将探讨如何利用 Verilog HDL 实现一个 16×16 点阵字符显示功能。16×16 点阵显示器由 16 行和 16 列的像素组成,共需 256 个二进制位来控制每个像素的亮灭,常用于简单字符或图形显示。 要实现这一功能,首先需要掌握基本的逻辑门(如与门、或门、非门、与非门、或非门等)和组合逻辑电路,以及寄存器和计数器等时序逻辑电路。设计的核心是构建一个模块,该模块接收字符输入(如 ASCII 码),将其转换为 16×16 的二进制位流,进而驱动点阵的 LED 灯。具体而言,该模块包含以下部分:一是输入接口,通常为 8 位的 ASCII 码输入,用于指定要显示的字符;二是内部存储,用于存储字符对应的 16×16 点阵数据,可采用寄存器或分布式 RAM 实现;三是行列驱动逻辑,将点阵数据转换为驱动 LED 矩阵的信号,包含 16 个行输出线和 16 个列使能信号,按特定顺序选通点亮对应 LED;四是时序控制,通过计数器逐行扫描,按顺序控制每行点亮;五是复用逻辑(可选),若点阵支持多颜色或亮度等级,则需额外逻辑控制像素状态。 设计过程中,需用 Verilog 代码描述上述逻辑,并借助仿真工具验证功能,确保能正确将输入字符转换为点阵显示。之后将设计综合到目标 FPGA 架构,通过配置 FPGA 实现硬件功能。实际项目中,“led_lattice”文件可能包含 Verilog 源代码、测试平台文件、配置文件及仿真结果。其中,测试平台用于模拟输入、检查输出,验证设计正确性。掌握 Verilog HDL 实现 16×16 点阵字符显示,涉及硬件描述语言基础、数字逻辑设计、字符编码和 FPGA 编程等多方面知识,是学习
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