PCI板卡金手指尺寸和定义规范

一、PCI

PCI接口分为32bit和64bit两种,32bit就是一般台式机使用的普通的pci接口(图一、图三),64bit接口比32bit接口长一些一般只出现在服务器上(图四、图五)。32bit和64bit都有5v和3.3v电压两种,5v电压的是PCI2.1标准的时钟频率为33MHz,3.3v电压的是PCI2.2标准以后出现的可以工作在66MHz的时钟频率上。不过现在一般来说,卡和插槽都做成可以同时兼容两种电压的版本,也都有防插错设计,只要能插上都是可以工作,不过工作在哪种时钟频率上就要分析一下了。32bit的pci接口生命力很顽强,即使现在最新的主板上也会留几个插槽,不过64bit的PCI接口好像在服务器上也是昙花一现基本被淘汰了。

1、32Bit PCI

 

图一 32Bit 5v pci 网卡

图二 最上边是兼容5v和3.3v,中间是5v电压的,最下边的是3.3v电压的

图三 传统的5v PCI 插槽

2、64Bit PCI

64bit比32bit要长一些,也分为5v,3.3v,和兼容两种电压的

图四

图五 64bit PCI插槽

二、PCI-X

    PCI-X在外形上和64bit的PCI基本上是一样的,但是它们使用的是不同的标准,PCI-X的插槽可以兼容PCI的卡(通过针脚区分),PCI-X也是共享总线的,插多个设备传输速率会下降。PCI-X一般只出现在服务器主板上,不过现在也逐步被PCI-E取代,很多厂商的服务器都已经不提供PCI-X的插槽了。

图六

图七

 

 

三、PCI-E

      PCI Express是INTEL提出的新一代的总线接口,PCI Express采用了目前业内流行的点对点串行连接,比起PCI以及更早期的计算机总线的共享并行架构,每个设备都有自己的专用连接,不需要向整个总线请求带宽,而且可以把数据传输率提高到一个很高的频率,达到PCI所不能提供的高带宽。相对于传统PCI总线在单一时间周期内只能实现单向传输,PCI Express的双单工连接能提供更高的传输速率和质量。PCI-E插槽是可以向下兼容的,比如PCI-E 16X插槽可以插8X、4X、1X的卡。现在的服务器一般都会提供多个8X、4X的接口,已取代以前的PCI-X接口。

图八 从上到下依次是PCI-E 4X、PCI-E 16X、PCI-E 1X

图九 PCI-E 1X的网卡

图十 PCI-E 4X的双端口网卡

图十一 PCI-E 16X的显卡

四、总结

标准总线时钟传输速度
PCI 32bit32bit33MHz
66MHz
133Mb/s
266Mb/s
PCI 64bit64bit33MHz
66MHz
266Mb/s
533Mb/s
PCI-X64bit66MHz
100MHz
133MHz
533Mb/s
800Mb/s
1066Mb/s
PCI-E X18bit2.5GHz512Mb/s(双工)
PCI-E X48bit2.5GHz2Gb/s(双工)
PCI-E X88bit2.5GHz4Gb/s(双工)
PCI-E X168bit2.5GHz8Gb/s(双工)

 

1x,4x,8x,16x的PCI-E卡及插槽规格兼容简述

PCI-E是PCI Express的简称。PCI Express 2.0是新一代的总线接口技术。(也不会新多久了,会被PCI Express 3.0规范取代)PCI Express的接口根据总线位宽不同而有所差异,包括X1、X4、X8以及X16(X2模式将用于内部接口而非插槽模式)。较短的PCI Express卡可以插入较长的PCI Express插槽中使用。PCI Express接口能够支持热拔插。(没插拔玩过)PCI Express卡支持的三种电压分别为+3.3V、3.3Vaux以及+12V。用于取代AGP接口的PCI Express接口位宽为X16,将能够提供5GB/s的带宽,且支持双向数据传输,即便有编码上的损耗但也远远超过AGP 8X的2.1GB/s的带宽。

PCI Express规格从1条通道连接到32条通道连接,有非常强的伸缩性,以满足不同系统设备对数据传输带宽不同的需求。例如,PCI Express X1规格支持双向数据传输,每向数据传输带宽250MB/s,PCI Express X1已经可以满足主流声效芯片、网卡芯片和存储设备对数据传输带宽的需求,但是远远无法满足图形芯片对数据传输带宽的需求。因此,必须采用PCI Express X16,即16条点对点数据传输通道连接来取代传统的AGP总线,优势差异十分明显。

尽管PCI Express技术规格允许实现X1(250MB/秒),X2,X4,X8,X12,X16和X32通道规格,但是依目前形式来看,PCI Express X16将成为PCI Express主流规格,同时芯片组厂商将在南桥芯片当中添加对PCI Express X1的支持,在北桥芯片当中添加对PCI Express X16的支持。除去提供极高数据传输带宽之外,PCI Express因为采用串行数据包方式传递数据,所以PCI Express接口每个针脚可以获得比传统I/O标准更多的带宽,这样就可以降低PCI Express设备生产成本和体积。另外,PCI Express也支持高阶电源管理,支持热插拔,支持数据同步传输,为优先传输数据进行带宽优化。

上图中的主板1x/4x/8x(橙色)/16x插槽均有

PCI-E的短卡均可以插在长插槽上,长卡方面除16X的板卡由于太长不能插到1X/4X的槽里,其它也可互相兼容。(长卡插短插槽未实际测试)实现插槽和板卡之间的全兼容。

二、PCI金手指定义

PCI 标准 32位/64位 接口卡大概就是下面的样子,由于pci接口拥有无与伦比的传输速度,在各个方面得到了非常广泛的应用
 ----------------------------------------------------------------
|    PCI         元件侧 (B面)                                  |
|                                                                |
|                                                                |
|                                                                |
|    ____     32 位引脚部分                    64 位引脚部分  ___|
|___|    |||||||--|||||||||||||||||--|||||||--||||||||||||||
         ^     ^  ^               ^  ^     ^  ^            ^
       b01   b11  b14           b49  b52 b62  b63          b94
PCI 5V 32/64位卡
|                                                optional        |
|    ____     32 位引脚部分                    64 位引脚部分  ___|
|___|    ||||||||||||||||||||||||||--|||||||--||||||||||||||
PCI 3.3V 32/64位卡
|                                                optional        |
|    ____     32 位引脚部分                    64 位引脚部分  ___|
|___|    |||||||--||||||||||||||||||||||||||--||||||||||||||

pci总线信号定义

 

Pin

+5V

+3.3V

Universal

Description

A1

TRST

 

 

Test Logic Reset

A2

+12V

 

 

+12 VDC

A3

TMS

 

 

Test Mde Select

A4

TDI

 

 

Test Data Input

A5

+5V

 

 

+5 VDC

A6

INTA

 

 

Interrupt A

A7

INTC

 

 

Interrupt C

A8

+5V

 

 

+5 VDC

A9

RESV01

 

 

Reserved VDC

A10

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

A11

RESV03

 

 

Reserved VDC

A12

GND03

(OPEN)

(OPEN)

Ground or Open (Key)

A13

GND05

(OPEN)

(OPEN)

Ground or Open (Key)

A14

RESV05

 

 

Reserved VDC

A15

RESET

 

 

Reset

A16

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

A17

GNT

 

 

Grant PCI use

A18

GND08

 

 

Ground

A19

RESV06

 

 

Reserved VDC

A20

AD30

 

 

Address/Data 30

A21

+3.3V01

 

 

+3.3 VDC

A22

AD28

 

 

Address/Data 28

A23

AD26

 

 

Address/Data 26

A24

GND10

 

 

Ground

A25

AD24

 

 

Address/Data 24

A26

IDSEL

 

 

Initialization Device Select

A27

+3.3V03

 

 

+3.3 VDC

A28

AD22

 

 

Address/Data 22

A29

AD20

 

 

Address/Data 20

A30

GND12

 

 

Ground

A31

AD18

 

 

Address/Data 18

A32

AD16

 

 

Address/Data 16

A33

+3.3V05

 

 

+3.3 VDC

A34

FRAME

 

 

Address or Data phase

A35

GND14

 

 

Ground

A36

TRDY

 

 

Target Ready

A37

GND15

 

 

Ground

A38

STOP

 

 

Stop Transfer Cycle

A39

+3.3V07

 

 

+3.3 VDC

A40

SDONE

 

 

Snoop Done

A41

SBO

 

 

Snoop Backoff

A42

GND17

 

 

Ground

A43

PAR

 

 

Parity

A44

AD15

 

 

Address/Data 15

A45

+3.3V10

 

 

+3.3 VDC

A46

AD13

 

 

Address/Data 13

A47

AD11

 

 

Address/Data 11

A48

GND19

 

 

Ground

A49

AD9

 

 

Address/Data 9

A52

C/BE0

 

 

Command, Byte Enable 0

A53

+3.3V11

 

 

+3.3 VDC

A54

AD6

 

 

Address/Data 6

A55

AD4

 

 

Address/Data 4

A56

GND21

 

 

Ground

A57

AD2

 

 

Address/Data 2

A58

AD0

 

 

Address/Data 0

A59

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

A60

REQ64

 

 

Request 64 bit ???

A61

VCC11

 

 

+5 VDC

A62

VCC13

 

 

+5 VDC

 

 

 

 

 

A63

GND

 

 

Ground

A64

C/BE[7]#

 

 

Command, Byte Enable 7

A65

C/BE[5]#

 

 

Command, Byte Enable 5

A66

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

A67

PAR64

 

 

Parity 64 ???

A68

AD62

 

 

Address/Data 62

A69

GND

 

 

Ground

A70

AD60

 

 

Address/Data 60

A71

AD58

 

 

Address/Data 58

A72

GND

 

 

Ground

A73

AD56

 

 

Address/Data 56

A74

AD54

 

 

Address/Data 54

A75

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

A76

AD52

 

 

Address/Data 52

A77

AD50

 

 

Address/Data 50

A78

GND

 

 

Ground

A79

AD48

 

 

Address/Data 48

A80

AD46

 

 

Address/Data 46

A81

GND

 

 

Ground

A82

AD44

 

 

Address/Data 44

A83

AD42

 

 

Address/Data 42

A84

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

A85

AD40

 

 

Address/Data 40

A86

AD38

 

 

Address/Data 38

A87

GND

 

 

Ground

A88

AD36

 

 

Address/Data 36

A89

AD34

 

 

Address/Data 34

A90

GND

 

 

Ground

A91

AD32

 

 

Address/Data 32

A92

RES

 

 

Reserved

A93

GND

 

 

Ground

A94

RES

 

 

Reserved

 

 

 

 

 

B1

-12V

 

 

-12 VDC

B2

TCK

 

 

Test Clock

B3

GND

 

 

Ground

B4

TDO

 

 

Test Data Output

B5

+5V

 

 

+5 VDC

B6

+5V

 

 

+5 VDC

B7

INTB

 

 

Interrupt B

B8

INTD

 

 

Interrupt D

B9

PRSNT1

 

 

Reserved

B10

RES

 

 

+V I/O (+5 V or +3.3 V)

B11

PRSNT2

 

 

??

B12

GND

(OPEN)

(OPEN)

Ground or Open (Key)

B13

GND

(OPEN)

(OPEN)

Ground or Open (Key)

B14

RES

 

 

Reserved VDC

B15

GND

 

 

Reset

B16

CLK

 

 

Clock

B17

GND

 

 

Ground

B18

REQ

 

 

Request

B19

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

B20

AD31

 

 

Address/Data 31

B21

AD29

 

 

Address/Data 29

B22

GND

 

 

Ground

B23

AD27

 

 

Address/Data 27

B24

AD25

 

 

Address/Data 25

B25

+3.3V

 

 

+3.3VDC

B26

C/BE3

 

 

Command, Byte Enable 3

B27

AD23

 

 

Address/Data 23

B28

GND

 

 

Ground

B29

AD21

 

 

Address/Data 21

B30

AD19

 

 

Address/Data 19

B31

+3.3V

 

 

+3.3 VDC

B32

AD17

 

 

Address/Data 17

B33

C/BE2

 

 

Command, Byte Enable 2

B34

GND13

 

 

Ground

B35

IRDY

 

 

Initiator Ready

B36

+3.3V06

 

 

+3.3 VDC

B37

DEVSEL

 

 

Device Select

B38

GND16

 

 

Ground

B39

LOCK

 

 

Lock bus

B40

PERR

 

 

Parity Error

B41

+3.3V08

 

 

+3.3 VDC

B42

SERR

 

 

System Error

B43

+3.3V09

 

 

+3.3 VDC

B44

C/BE1

 

 

Command, Byte Enable 1

B45

AD14

 

 

Address/Data 14

B46

GND18

 

 

Ground

B47

AD12

 

 

Address/Data 12

B48

AD10

 

 

Address/Data 10

B49

GND20

 

 

Ground

B50

(OPEN)

GND

(OPEN)

Ground or Open (Key)

B51

(OPEN)

GND

(OPEN)

Ground or Open (Key)

B52

AD8

 

 

Address/Data 8

B53

AD7

 

 

Address/Data 7

B54

+3.3V12

 

 

+3.3 VDC

B55

AD5

 

 

Address/Data 5

B56

AD3

 

 

Address/Data 3

B57

GND22

 

 

Ground

B58

AD1

 

 

Address/Data 1

B59

VCC08

 

 

+5 VDC

B60

ACK64

 

 

Acknowledge 64 bit ???

B61

VCC10

 

 

+5 VDC

B62

VCC12

 

 

+5 VDC

 

 

 

 

 

B63

RES

 

 

Reserved

B64

GND

 

 

Ground

B65

C/BE[6]#

 

 

Command, Byte Enable 6

B66

C/BE[4]#

 

 

Command, Byte Enable 4

B67

GND

 

 

Ground

B68

AD63

 

 

Address/Data 63

B69

AD61

 

 

Address/Data 61

B70

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

B71

AD59

 

 

Address/Data 59

B72

AD57

 

 

Address/Data 57

B73

GND

 

 

Ground

B74

AD55

 

 

Address/Data 55

B75

AD53

 

 

Address/Data 53

B76

GND

 

 

Ground

B77

AD51

 

 

Address/Data 51

B78

AD49

 

 

Address/Data 49

B79

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

B80

AD47

 

 

Address/Data 47

B81

AD45

 

 

Address/Data 45

B82

GND

 

 

Ground

B83

AD43

 

 

Address/Data 43

B84

AD41

 

 

Address/Data 41

B85

GND

 

 

Ground

B86

AD39

 

 

Address/Data 39

B87

AD37

 

 

Address/Data 37

B88

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

B89

AD35

 

 

Address/Data 35

B90

AD33

 

 

Address/Data 33

B91

GND

 

 

Ground

B92

RES

 

 

Reserved

B93

RES

 

 

Reserved

B94

GND

 

 

Ground


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Traditional multi-drop, parallel bus technology is approaching its practical performance limits. It is clear that balancing system performance requires I/O bandwidth to scale with processing and application demands. There is an industry mandate to re-engineer I/O connectivity within cost constraints. PCI Express comprehends the many I/O requirements presented across the spectrum of computing and communications platforms, and rolls them into a common scalable and extensible I/O industry specification. Alongside these increasing performance demands, the enterprise server and communications markets have the need for improved reliability, security, and quality of service guarantees. This specification will therefore be applicable to multiple market segments. Technology advances in high-speed, point-to-point interconnects enable us to break away from the bandwidth limitations of multi-drop, parallel buses. The PCI Express basic physical layer consists of a differential transmit pair and a differential receive pair. Dual simplex data on these point-to-point connections is self-clocked and its bandwidth increases linearly with interconnect width and frequency. PCI Express takes an additional step of including a message space within its bus protocol that is used to implement legacy “side- band” signals. This further reduction of signal pins produces a very low pin count connection for components and adapters. The PCI Express Transaction, Data Link, and Physical Layers are optimized for chip-to-chip and board-to-board interconnect applications. An inherent limitation of today’s PCI-based platforms is the lack of support for isochronous data delivery, an attribute that is especially important to streaming media applications. To enable these emerging applications, PCI Express adds a virtual channel mechanism. In addition to use for support of isochronous traffic, the virtual channel mechanism provides an infrastructure for future extensions in supporting new applications. By adhering to the PCI Software Model, today’s applications are easily migrated even as emerging applications are enabled.
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