FPGA串口通信

串口发送8位数据

module uart_byte_tx(
	Rst_n,
	Clk,
	Data,
	Send_en,
	uart_tx,
	Baud_set,
	Tx_done
	
    );
	
	input Rst_n;
	input Clk;
	input [7:0]Data;
	input Send_en;
	input [2:0]Baud_set;
	
	output reg uart_tx;
	output reg Tx_done;
	
	
	
	reg [15:0]bps_DR;
	always@(*)
	begin
		case(Baud_set)
			0:bps_DR = 1000000000/9600/20;
			1:bps_DR = 1000000000/19200/20;
			2:bps_DR = 1000000000/38400/20;
			3:bps_DR = 1000000000/57600/20;
			4:bps_DR = 1000000000/115200/20;
			default:bps_DR = 1000000000/9600/20;
		endcase
	end	
		
	
	reg [15:0]div_cnt;	
	always@(posedge Clk or negedge Rst_n)
	begin
		if(!Rst_n)
			div_cnt <= 0;
		else if(Send_en)
		begin
			if(div_cnt == bps_DR - 1)
				div_cnt <= 0;
			else	
				div_cnt <= div_cnt + 1;
		end
		else
			div_cnt <= 0;
	end
	
	reg [3:0]bps_cnt;
	always@(posedge Clk or negedge Rst_n)
	begin
		if(!Rst_n)
			bps_cnt <= 0;
		else if(Send_en)
			begin
				if(div_cnt == 1)
					begin
						if(bps_cnt == 11)
							bps_cnt <= 0;
						else	
							bps_cnt <= bps_cnt + 1; 
					end
			end
		else
			bps_cnt <= 0;
	end
	
	
	always@(posedge Clk or negedge Rst_n)
	begin
		if(!Rst_n)
		begin
			uart_tx <= 1;
			Tx_done <= 0;
		end
		else
			case(bps_cnt)
				1: begin uart_tx <= 0;Tx_done <= 0;end			
				2: uart_tx <= Data[0];
				3: uart_tx <= Data[1];
				4: uart_tx <= Data[2];
				5: uart_tx <= Data[3];
				6: uart_tx <= Data[4];
				7: uart_tx <= Data[5];
				8: uart_tx <= Data[6];
				9: uart_tx <= Data[7];
				10:uart_tx <= 1;
				11:begin uart_tx <= 1;Tx_done <= 1;end				
				default:uart_tx <= 1;
			endcase	
	end
	
	reg bps_clk;
	always@(posedge Clk or negedge Rst_n)
	begin
		if(!Rst_n)	
			bps_clk <= 0;
		else if(div_cnt == 1)
			bps_clk <= 1;
		else			
			bps_clk <= 0;
	end
	
endmodule

testbench测试模块

`timescale 1ns / 1ps

module uart_byte_tx_tb();
	
	reg Rst_n;
	reg Clk;
	reg [7:0]Data;
	reg Send_en;
	reg [2:0]Baud_set;
	
	wire uart_tx;
	wire Tx_done;
	
	uart_byte_tx uart_byte_tx(
	.Rst_n(Rst_n),
	.Clk(Clk),
	.Data(Data),
	.Send_en(Send_en),
	.uart_tx(uart_tx),
	.Baud_set(Baud_set),
	.Tx_done(Tx_done)
	
    );
	
	initial Clk = 1;
	always #10 Clk = ~Clk;
	
	initial begin		
		Rst_n = 0;
		Data = 0;
		Send_en = 0;
		Baud_set = 4;
		#201;
		Rst_n = 1;
		#100;
		Data = 8'h57;
		Send_en = 1;
		#20;
		@(posedge Tx_done);
		Send_en = 0;
		#20000;
		
		Data = 8'h75;
		Send_en = 1;
		#20;
		@(posedge Tx_done);
		Send_en = 0;
		#20000;
		
		$stop;
	
	end

测试波形