verilog基础(二选一多路器、三八译码器)

1.二选一多路器

module mux_2(
  a,
  b,
  sel,
  out
);
  input a;
  input b;
  input sel;
  output out;

  assign out = (sel==1)?a:b;//assign 用于连续性赋值语句

endmodule

testbench：

`timescale 1ns/1ns

module mux_2_tb();

  reg a;
  reg b;
  reg sel;
  wire out;

mux_2 mux_2(
  .a(a),
  .b(b),
  .sel(sel),
  .out(out)
);

initial begin
  a = 0;b = 0;sel = 0;
  #200;
  a = 0;b = 0;sel = 1;
  #200;
  a = 0;b = 1;sel = 0;
  #200;  
  a = 0;b = 1;sel = 1;
  #200;
  a = 1;b = 0;sel = 0;
  #200;
  a = 1;b = 0;sel = 1;
  #200;
  a = 1;b = 1;sel = 0;
  #200;
  a = 1;b = 1;sel = 1;
  #200;

  $stop;
end

endmodule

2.3-8译码器

module decoder3_8(
  //端口列表
  a,
  b,
  c,
  out

);
  //端口类型定义
  input a;
  input b;
  input c;
  output reg[7:0] out;
  //描述逻辑关系
  always@(*)begin 
  case({a,b,c}):
	3'b000:out = 8'b0000_0001;
	3'b001:out = 8'b0000_0010;
	3'b010:out = 8'b0000_0100;
	3'b011:out = 8'b0000_1000;
	3'b100:out = 8'b0001_0000;
	3'b101:out = 8'b0010_0000;
	3'b110:out = 8'b0100_0000;
	3'b111:out = 8'b1000_0000;
	endcase
  end
	
endmodule

testbench：

`timescale 1ns/1ns
module decoder3_8_tb();
//定义端口激励，输入为reg型，输出为wire型

	reg a;
	reg b;
	reg c;
	wire out;

decoder3_8 decoder3_8(
//连线
  .a(a),
  .b(b),
  .c(c),
  .out(out)
);
//产生激励
	initial begin
		a = 0;b = 0;c = 0;
		#200;
		a = 0;b = 0;c = 1;
		#200;
		a = 0;b = 1;c = 0;
		#200;
		a = 0;b = 1;c = 1;
		#200;
		a = 1;b = 0;c = 0;
		#200;
		a = 1;b = 0;c = 1;
		#200;
		a = 1;b = 1;c = 0;
		#200;
		a = 1;b = 1;c = 1
		#200;
		$stop;			
	end

endmodule