module spi_ctrl (
input wire sclk,//50M
input wire rst_n
//input wire work_en,
//output wire spi_clk,//主机模式
//output wire spi_sdi,
//output wire spi_csn,
//input wire spi_sdo
);
//parameter IDLE = 5'b0_0001;//状态机
//parameter WAIT = 5'b0_0010;
//parameter R_MEM= 5'b0_0100;
//parameter W_REG= 5'b0_1000;
//parameter STOP = 5'b1_0000;
parameter H_DIV_CYC = 5'd25-1;
reg [4:0] state;
reg [4:0] div_cnt;
reg clk_p;
always @(posedge sclk or negedge rst_n)
if (rst_n == 0)
div_cnt <= 5'd0;
else if (div_cnt == H_DIV_CYC)
div_cnt <= 'b0;
else div_cnt <= div_cnt +1'b1;
always @(posedge sclk or negedge rst_n)
if (rst_n == 0)
clk_p <= 'b0;
else if (div_cnt == H_DIV_CYC)
clk_p <= ~clk_p;
//改进的写法:将上述的两个always模块合并在一起会有什么样的综合,以及分开写的好处或者坏处????
//2015年7月24日 16:13:43
//always @(posedge sclk or negedge rst_n)
// if (rst_n == 0)
// begin
// div_cnt <= 5'd0;
// clk_p <= 'b0;
// end
// else if (div_cnt == H_DIV_CYC)
// begin
// clk_p <= ~clk_p;
// div_cnt <= 'b0;
// end
// else div_cnt <= div_cnt +1'b1;
endmodule
input wire sclk,//50M
input wire rst_n
//input wire work_en,
//output wire spi_clk,//主机模式
//output wire spi_sdi,
//output wire spi_csn,
//input wire spi_sdo
);
//parameter IDLE = 5'b0_0001;//状态机
//parameter WAIT = 5'b0_0010;
//parameter R_MEM= 5'b0_0100;
//parameter W_REG= 5'b0_1000;
//parameter STOP = 5'b1_0000;
parameter H_DIV_CYC = 5'd25-1;
reg [4:0] state;
reg [4:0] div_cnt;
reg clk_p;
always @(posedge sclk or negedge rst_n)
if (rst_n == 0)
div_cnt <= 5'd0;
else if (div_cnt == H_DIV_CYC)
div_cnt <= 'b0;
else div_cnt <= div_cnt +1'b1;
always @(posedge sclk or negedge rst_n)
if (rst_n == 0)
clk_p <= 'b0;
else if (div_cnt == H_DIV_CYC)
clk_p <= ~clk_p;
//改进的写法:将上述的两个always模块合并在一起会有什么样的综合,以及分开写的好处或者坏处????
//2015年7月24日 16:13:43
//always @(posedge sclk or negedge rst_n)
// if (rst_n == 0)
// begin
// div_cnt <= 5'd0;
// clk_p <= 'b0;
// end
// else if (div_cnt == H_DIV_CYC)
// begin
// clk_p <= ~clk_p;
// div_cnt <= 'b0;
// end
// else div_cnt <= div_cnt +1'b1;
endmodule