一个比较常用的modelsim仿真脚本（verilog）

1   # create work library
2   vlib work
3  
4   # compile
5   vlog my_dcfifo . v
6   vlog my_dcfifo_tb . v
7  
8   # simulate
9   vsim -L C: / altera / 81 / modelsim_ae / altera / verilog / 220model -L C: / altera / 81 / modelsim_ae / altera / verilog / altera_mf work . my_dcfifo_tb
10  
11   # probe signals
12   add wave sim: / my_dcfifo_tb / aclr
13   add wave sim: / my_dcfifo_tb / wrclk
14   add wave sim: / my_dcfifo_tb / wrreq
15   add wave -literal -radix decimal sim: / my_dcfifo_tb / data
16   add wave sim: / my_dcfifo_tb / wrfull
17   add wave sim: / my_dcfifo_tb / rdclk
18   add wave sim: / my_dcfifo_tb / rdreq
19   add wave -literal -radix decimal sim: / my_dcfifo_tb / q
20   add wave sim: / my_dcfifo_tb / rdempty
21   add wave -literal -radix decimal sim: / my_dcfifo_tb / rdusedw
22  
23   # 300  ns
24   run   300  ns