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`timescale 1ns / 1ps Company: // Engineer: // // Create Date: 13:59:59 05/04/2017 // Design Name: // Module Name: fre // Project Name: // Target Devices: // Tool versions: // Description: Dependencies: Revision: // Revision 0.01 - File Created// Additional Comments: module fre( input clock,input reset,output [3:0] led);//input clock,reset;//output led;wire clk_50;wire clk_100;wire clk_150;wire clk_200;wire sys_rst_n;reg[3:0] led_buf=0;assign led=led_buf;free_50_100_150_200 uut_fre (// Clock in ports .CLK_IN1(clock), // IN // Clock out ports .CLK_OUT1(clk_50), // OUT .CLK_OUT2(clk_100), // OUT .CLK_OUT3(clk_150), // OUT .CLK_OUT4(clk_200), // OUT // Status and control signals .RESET(reset),// IN .LOCKED(sys_rst_n) ); // OUTalways @(posedge clk_50)beginif(reset)beginled_buf[0]<=0;endelseled_buf[0]<=!led_buf[0];endalways @(posedge clk_100)beginif(reset)led_buf[1]<=0;elseled_buf[1]<=!led_buf[1];endalways @(posedge clk_150)beginif(reset)led_buf[2]<=0;elseled_buf[2]<=!led_buf[2];endalways @(posedge clk_200)beginif(reset)led_buf[3]<=0;elseled_buf[3]<=!led_buf[3];end endmodule

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