第一次用verilog调试串口（发送、接收）

1、首先是发送，程序如下

`timescale 1ns / 1ps

module send(in_data,out_data,en,clk); 
			
input clk;
input[7:0] in_data;
input en;
output reg out_data;

reg [12:0] timer;
reg[7:0]  in_buffer;
//reg tx_flag;



always @(posedge clk) 
begin 
	if(en==1) 
	  begin
		if(timer==20)
		in_buffer<=in_data; 
		//in_buffer<=8'b00000010;
		if(timer<4774)    
				timer<=timer+1'b1;
				else
				begin
					timer<=0;
					in_buffer<=0;
				end
	  end		
end
 
always @(posedge clk)
   begin
	if(en==1)
	begin
	
       case(timer)
           
           13'd0:
				begin
                 out_data<=0;
				 end
           13'd434: 
                 out_data<=in_buffer[0];//?????????
           13'd868:
                 out_data<=in_buffer[1];
           13'd1302:
                 out_data<=in_buffer[2];
           13'd1736:
                 out_data<=in_buffer[3];
           13'd2170:
                 out_data<=in_buffer[4];
           13'd2604:
                 out_data<=in_buffer[5];           
           13'd3038:
                 out_data<=in_buffer[6];
           13'd3472:
                 out_data<=in_buffer[7];
           13'd3906:
                 out_data<=0;
           13'd4340: 
				        begin		   
                 out_data<=1'b1;
				       end
       endcase    
    end
else
out_data<=1'bz;	 
   end  
   
endmodule

2、然后是接收

`timescale 1ns / 1ps


module rx(data_in,
          en,
          rx_finish,
          clk,
          data_out,
          rst
);
input data_in;
input clk,en,rst;//
output  rx_finish;
reg rx_finish;
output reg[7:0]  data_out;
reg[7:0] data_buffer;
reg[13:0] timer=0;
reg[7:0] time1=0;
reg[8:0] time2;
reg[3:0] i;  
(* KEEP =  "TRUE" *) reg  T=0;//前面括号是为了在chipscope中能找到改信号，以免被优化掉


always @(posedge clk)//use for chipscope，chipscope的触发信号产生
begin
time1<=time1+1'd1;
i