LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY detector IS
PORT(clk,x: IN STD_LOGIC;
mk: OUT STD_LOGIC);
END detector;
ARCHITECTURE xdetector OF detector IS
TYPE states IS(s0,s1,s2,s3,s4,s5,s6,s7);
SIGNAL state: states;
BEGIN
PROCESS(x,state)
BEGIN
IF rising_edge(clk) THEN
CASE state IS
WHEN s0 => mk<='0';
IF(x='1') THEN
state<=s1;
ELSE
state<=s0;
END IF;
WHEN s1 => mk<='0';
IF(x='1') THEN
state<=s2;
ELSE
state<=s0;
END IF;
WHEN s2 => mk<='0';
IF(x='1') THEN
state<=s2;
ELSE
state<=s3;
END IF;
WHEN s3 => mk<='0';