MPSOC DP输出配置笔记

原创已于 2023-10-09 10:15:22 修改

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#笔记

于 2023-08-27 16:37:31 首次发布

版本信息如下
Petalinux 2021.2
Vivado 2021.2
要修改system-user.dtsi指定psgtr的时钟信息
参考 https://support.xilinx.com/s/article/76568?language=en_US

/include/ "system-conf.dtsi"
/ {
    lvds_0: lvds_0 { 
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <27000000>;
    };

    lvds_1: lvds_1 { 
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <150000000>;
    };

    lvds_2: lvds_2 { 
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <100000000>;
    };
};

&psgtr {
    status = "okay";
    clocks = <&lvds_0>, <&lvds_1>, <&lvds_2>;
    clock-names = "ref0", "ref1", "ref2";
};

其中 27M 是接的 PS_MGTREFCLK0P/N，给DP用的。
150M是给SATA用的，100M是给USB用的。

如果不配这个，会提示类似

[    3.831756] xilinx-zynqmp-dpdma fd4c0000.dma-controller: Xilinx DPDMA engine is probed
[    3.850861] xilinx-psgtr fd400000.phy: Invalid reference clock number 0
[    3.857470] zynqmp-display fd4a0000.display: failed to get PHY lane 0
[    3.863919] zynqmp-display: probe of fd4a0000.display failed with error -22

在Block Design中正确分配 VPLL
参考 https://support.xilinx.com/s/article/69764?language=en_US

Note: VPLL should be used only for Display Port (DP_VIDEO)

DDR PLL (DPLL): Mainly used to generate clocks for the DDR controller.
APU PLL (APLL): Mainly used to generate clocks for the APU.
RPU PLL (RPLL): Mainly used to generate clocks for the RPU.
I/O PLL (IOPLL): Mainly used to generate clocks the peripheral I/Os.
Video PLL (VPLL): generates clocks for the video blocks used in the PS subsystem.

VPLL只给DP_VIDEO用，要不然动态改变DP输出分辨率的时候可能有问题。
DP_AUDIO也有类似问题，但是一般可以固定输出48K就不变了。