大量的verilog源代码

 

Verilog HDL 程序举例

一，基本组合逻辑功能：

双向管脚（clocked bidirectional pin）

Verilog HDL: Bidirectional Pin

 

This example implements a clockedbidirectional pin in Verilog HDL.

The value of OE determines whether bidir isan input, feeding in inp, or a tri-state, driving out the value b.

 

 

bidir.v

 

module bidirec (oe, clk, inp, outp, bidir);

 

// Port Declaration

 

input  oe;

input  clk;

input  [7:0] inp;

output [7:0] outp;

inout  [7:0] bidir;

 

reg    [7:0] a;

reg    [7:0] b;

 

assign bidir = oe ? a : 8'bZ ;

assign outp = b;

 

// Always Construct

 

always @ (posedge clk)

begin

       b <= bidir;

       a <= inp;

end

 

endmodule

 

 

多路选择器（MUX）

//

//-----------------------------------------------------------------------------------

// DESCRIPTION   : Multiplexer

//                  Code style: used casestatement

//                  Width of output terminal: 8

//                  Number of terminals: 4

//                  Output enable active: HIGH

//                  Output value of all bits whenenable not active: 0

 

//-----------------------------------------------------------------------------------

 

 

 

module mux(EN ,IN0 ,IN1 ,IN2 ,IN3 ,SEL ,OUT);

 

       input  EN ;

       input  [7:0] IN0 ,IN1 ,IN2 ,IN3 ;

       input  [1:0] SEL ;

 

       output [7:0] OUT ;

       reg  [7:0] OUT ;

 

 

       always @(SEL  or EN  or IN0 or IN1  or IN2  or IN3 )

       begin

                if (EN  == 0) OUT = {8{1'b0}};

               else

                        case (SEL )

                                0 : OUT  = IN0 ;

                                1 : OUT  = IN1 ;

                                2 : OUT  = IN2 ;

                                3 : OUT  = IN3 ;

                               default :OUT  = {8{1'b0}};

                        endcase

       end

 

endmodule

 

二进制到BCD码转换

//

//

//-----------------------------------------------------------------------------------

// DESCRIPTION   :  Binto Bcd converter

//                  Input (data_in) width : 4

//                  Output (data_out) width : 8

//                  Enable (EN) active : high

//-----------------------------------------------------------------------------------

 

 

 

module bin2bcd (data_in ,EN ,data_out );

 

input [3:0] data_in ;

input EN ;

output [7:0] data_out ;

reg [7:0] data_out ;

 

 

 

       always @(data_in or EN )

       begin

                data_out = {8{1'b0}};

                if (EN == 1)

                begin

                        case (data_in [3:1])

                                3'b000 :data_out [7:1] = 7'b0000000;

                                3'b001 :data_out [7:1] = 7'b0000001;

                                3'b010 :data_out [7:1] = 7'b0000010;

                                3'b011 :data_out [7:1] = 7'b0000011;

                                3'b100 :data_out [7:1] = 7'b0000100;

                                3'b101 :data_out [7:1] = 7'b0001000;

                                3'b110 : data_out[7:1] = 7'b0001001;

                                3'b111 :data_out [7:1] = 7'b0001010;

                                default :data_out [7:1] = {7{1'b0}};

                        endcase

                        data_out [0] = data_in[0];

               end

       end

 

endmodule

 

二进制到格雷码转换

//-----------------------------------------------------------------------------------

// DESCRIPTION   :  Binto gray converter

//                  Input (DATA_IN) width : 4

//                  Enable (EN) active : high

 

//-----------------------------------------------------------------------------------

 

 

module BIN2GARY (EN ,DATA_IN ,DATA_OUT );

 

       input EN ;

 

       input [3:0] DATA_IN ;

 

       output [3:0] DATA_OUT ;

 

       assign DATA_OUT [0] = (DATA_IN [0] ^ DATA_IN [1] ) && EN ;

       assign DATA_OUT [1] = (DATA_IN [1] ^ DATA_IN [2] ) && EN ;

       assign DATA_OUT [2] = (DATA_IN [2] ^ DATA_IN [3] ) && EN ;

       assign DATA_OUT [3] = DATA_IN [3] && EN ;

endmodule

 

 

7段译码器

 

//-----------------------------------------------------------------------------------

// DESCRIPTION   :  BIN to seven segments converter

//                   segment encoding

//                        a

//                      +---+

//                    f |   |b

//                      +---+  <- g

//                    e |   | c

//                      +---+

//                        d

//                  Enable (EN) active                : high

//                  Outputs (data_out)active         : low

//-----------------------------------------------------------------------------------

 

 

 

module bin27seg (data_in ,EN ,data_out );

 

       input [3:0] data_in ;

 

       input EN ;

 

       output [6:0] data_out ;

       reg [6:0] data_out ;

 

 

       always @(data_in or EN )

       begin

                data_out = 7'b1111111;

                if (EN == 1)

                        case (data_in )

                                4'b0000:data_out = 7'b1000000; // 0

                                4'b0001:data_out = 7'b1111001; // 1

                                4'b0010:data_out = 7'b0100100; // 2

                                4'b0011:data_out = 7'b0110000; // 3

                                4'b0100:data_out = 7'b0011001; // 4

                               4'b0101:data_out = 7'b0010010; // 5

                                4'b0110:data_out = 7'b0000011; // 6

                                4'b0111:data_out = 7'b1111000; // 7

                                4'b1000:data_out = 7'b0000000; // 8

                                4'b1001:data_out = 7'b0011000; // 9

                                4'b1010:data_out = 7'b0001000; // A

                                4'b1011:data_out = 7'b0000011; // b

                                4'b1100: data_out= 7'b0100111; // c

                                4'b1101:data_out = 7'b0100001; // d

                                4'b1110:data_out = 7'b0000110; // E

                                4'b1111:data_out = 7'b0001110; // F

                                default:data_out = 7'b1111111;

                        endcase

       end

 

endmodule

 

 

 

 

二，基本时序逻辑功能：

8位数据锁存器

//

//

//-----------------------------------------------------------------------------------

// DESCRIPTION   :  Flip-flopD type

//                  Width : 8

//                  CLK active : high

//                  CLR active : high

//                  CLR type : synchronous

//                  SET active : high

//                  SET type : synchronous

//                 LOAD active : high

//                  CE active : high

//-----------------------------------------------------------------------------------

 

 

module ffd (CLR , SET , CE , LOAD , DATA_IN, DATA_OUT , CLK );

input CLR , SET , CE , LOAD , CLK ;

input [7:0] DATA_IN ;

output [7:0] DATA_OUT ;

 

 

reg [7:0] DATA_OUT_TEMP;

 

       always @(posedge CLK )

       begin

                if (CE == 1'b1)

                        if (CLR == 1'b1)

                                DATA_OUT_TEMP ={8{1'b0}};

                        else if (SET == 1'b1)

                                DATA_OUT_TEMP ={8{1'b1}};

                        else if (LOAD == 1'b1)

                                DATA_OUT_TEMP =DATA_IN ;

       end

 

       assign DATA_OUT = DATA_OUT_TEMP;

 

endmodule

 

 

移位寄存器

//-----------------------------------------------------------------------------------

// DESCRIPTION   : Shift register

//                  Type : univ

//                  Width : 4

//                  Shift direction: right/left(right active high)

//

//                  CLK active : high

//                  CLR active : high

//                  CLR type : synchronous

//                  SET active : high

//                  SET type : synchronous

//                  LOAD active : high

//                  CE active : high

//                  SERIAL input : SI

//-----------------------------------------------------------------------------------

 

 

module shft_reg (CLR , SET , DIR , CE ,LOAD , DATA , SI , data_out , CLK );

input CLR , SET , CE , LOAD , DIR , SI ,CLK ;

input [3:0] DATA ;

output [3:0] data_out ;

 

 

 

reg [3:0] TEMP;

 

       always @(posedge CLK )

       begin

                if (CE == 1'b1)

                        if (CLR == 1'b1)

                                TEMP ={4{1'b0}};

                        else if (SET == 1'b1)

                                TEMP ={4{1'b1}};

                        else if (LOAD == 1'b1)

                                TEMP = DATA ;

                        else if (DIR == 1'b1)

                                TEMP = {SI ,TEMP [3:1]};

                        else

                                TEMP = {TEMP[2:0], SI };

       end

 

       assign data_out = TEMP;

endmodule

 

 

三，基本语法，元件例化与层次设计：

Verilog HDL: Creating a Hierarchical Design

 

This example describes how to create ahierarchical design using Verilog HDL.

The file top_ver.v is the top level, whichcalls the two lower level files bottom1.v and bottom2.v.

 

 

 

vprim.v

 

 

 

top_ver.v

 

module top_ver (q, p, r, out);

 

input    q, p, r;

output    out;

reg    out, intsig;

 

bottom1 u1(.a(q), .b(p), .c(intsig));

bottom2 u2(.l(intsig), .m(r), .n(out));

 

endmodule

 

 

--------------------------------------------------------------------------------

 

bottom1.v

 

module bottom1(a, b, c);

 

input    a, b;

output    c;

reg     c;

 

always

begin

    c<=a & b;

end

 

endmodule

 

 

--------------------------------------------------------------------------------

 

bottom2.v

 

module bottom2(l, m, n);

 

input    l, m;

output   n;

reg      n;

 

always

begin

    n<=l | m;

end

endmodule

 

 

 

 

四，状态机举例：

同步状态机

Verilog HDL: Synchronous State Machine

 

statem.v

 

module statem(clk, in, reset, out);

 

input clk, in, reset;

output [3:0] out;

 

reg [3:0] out;

reg [1:0] state;

 

parameter zero=0, one=1, two=2, three=3;

 

always @(state)

    begin

         case (state)

               zero:

                    out = 4'b0000;

               one:

                    out = 4'b0001;

               two:

                    out = 4'b0010;

               three:

                    out = 4'b0100;

               default:

                    out = 4'b0000;

         endcase

    end

 

always @(posedge clk or posedge reset)

    begin

         if (reset)

               state = zero;

         else

              case (state)

                    zero:

                         state = one;

                    one:

                         if (in)

                              state = zero;

                         else

                              state = two;

                    two:

                         state = three;

                    three:

                         state = zero;

               endcase

    end

 

endmodule