StstemVerilog中的约束 constraint

目录

1）关键字：extends

2）constraint_mode()

3）soft 约束有冲突的话，不报错，加soft的约束优先级变低，以另一个为准

4）对pre_randomize() 方法的集成

5）rand_mode(0)，关闭某个变量的随机，会保持初始值0.

6）inside关键字

7)  constraint -> ，相当于if前置条件

---

1）关键字：extends

        1、子类中对同一个变量的约束要和父类有交集，如果没有交集，会报error

class father;
  rand bit[10:0] data;
  constraint c_data{
    data >=10;
    data <=30;
  }
endclass

class son extends father;
  constraint c_son_data{
    data >=40;
    data <=100;
  }
endclass

module test;
  initial begin
    father fa;
    son    so;
    
    fa = new;
    so = new;
    
    fa.randomize();
    so.randomize();
    
    $display("canli test");
  end
endmodule

   运行结果：  

Error-[CNST-CIF] Constraints inconsistency failure
testbench.sv, 25
  Constraints are inconsistent and cannot be solved.
  Please check the inconsistent constraints being printed above and rewrite 
  them.

    注意哦，只要有交集就好咯，子类对某个变量的约束不需要是子集哦。

    如下所示，父类data范围10-30，子类data范围时29-250，有交集29-30，所以正常随机，随机出来是30.

class father;
  rand bit[10:0] data;
  constraint c_data{
    data >=10;
    data <=30;
  }
endclass

class son extends father;
  constraint c_son_data{
    data >=29;
    data <=250;
  }
endclass

module test;
  initial begin
    father fa;
    son    so;
    
    fa = new;
    so = new;
    
    fa.randomize();
    so.randomize();
    
    $display("father's data is %d",fa.data);
    $display("son's data is %d",so.data);
    
  end
endmodule

    运行结果

father's data is   14
son's data is   30

2）constraint_mode()

        1、constraint_mode(0)，关闭约束，也就是说，本来约束是10-30之间，关闭之后，就是0到2的10次方-1.