System Verilog激励发送和结果检查

本次展示输入何种激励和如何检查正确为主，其中DUT仍然保持不变，与[数字验证平台–从0到1（基于Verilog HDL）(https://blog.csdn.net/lfasdf/article/details/124984534?spm=1001.2014.3001.5502)一致

tinyalu_tb.sv文件

module top;

   typedef enum bit[2:0] {no_op  = 3'b000,
                          add_op = 3'b001, 
                          and_op = 3'b010,
                          xor_op = 3'b011,
                          mul_op = 3'b100,
                          rst_op = 3'b111} operation_t;
   byte         unsigned        A;
   byte         unsigned        B;
   bit          clk;
   bit          reset_n;
   wire [2:0]   op;
   bit          start;
   wire         done;
   wire [15:0]  result;
   operation_t  op_set;

   assign op = op_set;

   tinyalu DUT (.A, .B, .clk, .op, .reset_n, .start, .done, .result);

   initial begin
      clk = 0;
      forever begin
         #10;
         clk = ~clk;
      end
   end
   
   function operation_t get_op();
      bit [2:0] op_choice;
      op_choice = $random;
      case (op_choice)
        3'b000 : return no_op;
        3'b001 : return add_op;
        3'b010 : return and_op;
        3'b011 : return xor_op;
        3'b100 : return mul_op;
        3'b101 : return no_op;
        3'b110 : return rst_op;
        3'b111 : return rst_op;
      endcase // case (op_choice)
   endfunction : get_op

   function byte get_data();
      bit [1:0] zero_ones;
      zero_ones = $random;
      if (zero_ones == 2'b00)
        return 8'h00;
      else if (zero_ones == 2'b11)
        return 8'hFF;
      else
        return $random;
   endfunction : get_data

   always @(posedge done) begin : scoreboard
      shortint predicted_result;
      case (op_set)
        add_op: predicted_result = A + B;
        and_op: predicted_result = A & B;
        xor_op: predicted_result = A | B;
        mul_op: predicted_result = A * B;
      endcase // case (op_set)

      if ((op_set != no_op) && (op_set != rst_op)) begin
        if (predicted_result != result)
          $display ("Error: At %t ps A: %0h  B: %0h  op: %s result: %0h predicted_result: %0h",$time, A, B, op_set.name(), result, predicted_result);
        else
          $display("PASSED: At %t ps A: %0h  B: %0h  op: %s result: %0h",$time, A, B, op_set.name(), result);
      end

   end : scoreboard
   
   initial begin : tester
      reset_n = 1'b0;
      @(negedge clk);
      @(negedge clk);
      reset_n = 1'b1;
      start = 1'b0;
      repeat (1000) begin
         @(negedge clk);
         op_set = get_op();
         A = get_data();
         B = get_data();
         start = 1'b1;
         case (op_set) // handle the start signal
           no_op: begin 
              @(posedge clk);
              start = 1'b0;
           end
           rst_op: begin 
              reset_n = 1'b0;
              start = 1'b0;
              @(negedge clk);
              reset_n = 1'b1;
           end
           default: begin 
              wait(done);
              start = 1'b0;
           end
         endcase // case (op_set)
      end
      //$stop;
      //$exit;
      $finish();
   end : tester

   initial begin
       $fsdbDumpfile("tinyalu");
       $fsdbDumpvars;
       $vcdpluson;
   end
endmodule : top

top层结构

schematic图

打开波形–截图1（690ps处）

打开波形–截图1（750ps处）

run.log部分截图（包含690ps和750ps）