【FPGA】PWM_LED呼吸灯

PWM呼吸灯
调制PWM波占空比来实现LED从暗到亮，从亮到暗

// A code block
var foo = 'bar';

// An highlighted block
module pwm_led (
	input               	clk     ,
	input               	rst_n   ,
	input      		    	key_down,
	output  reg  	[3:0]  	led     
);
	
	parameter        			FRQ = 100_000; //频率100KHz  frequency
	    
	reg      		[16:0]      cnt_frq 	 ; //对应固定频率
	wire     		        	add_cnt_frq	 ; 
	wire     		        	end_cnt_frq	 ; 
	reg      		[16:0]      cnt_compare	 ; //对应占空比
	 
	reg                 		flag    	 ; //翻转的标志,实现由暗到亮，在从亮到按
	reg				  			led_flag	 ;


always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		led_flag <=0;
	end
	else if(key_down)begin
			led_flag <= ~led_flag;
		end
	else begin
			led_flag <= led_flag;
		end
end		
		

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt_frq <= 0;
    end
    else if(add_cnt_frq)begin
				 if(end_cnt_frq)begin
					 cnt_frq <= 0;
				end
				else begin
					 cnt_frq <= cnt_frq + 1;
				end
    end
end

assign add_cnt_frq = 1'b1;
assign end_cnt_frq = add_cnt_frq && cnt_frq == FRQ-1;//调整效果
	

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt_compare <= 0;
    end
    else if(cnt_compare >= FRQ)begin
            cnt_compare <= 0;
        end
        else if(end_cnt_frq) begin
            cnt_compare <= cnt_compare + 50;//步进可设置，调整效果
        end
			else begin
            cnt_compare <= cnt_compare ;
        end
end
	
//flag
always @(posedge clk or negedge rst_n)begin 
    if(!rst_n)begin
        flag <= 0;
    end 
    else if((flag == 0) && (cnt_compare >= FRQ))begin 
        flag <= 1'b1;
    end 
    else if((flag == 1'b1) && (cnt_compare >= FRQ))begin 
        flag <= 1'b0;
    end 
end
	
//led                   
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        led <= 8'b1111;  
    end                     
    else if(led_flag)begin
		 if(((flag == 1'b0) && cnt_frq < cnt_compare) || ((flag == 1'b1)
		  && (cnt_frq >cnt_compare)) )begin
			  led <= 8'b0000;
		 end
		 else begin
			  led <= 8'b1111;
		 end
	end
	else begin
	 led <= 8'b1111;
	end
end

endmodule