UART发送模块

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 波特率计算

  

module uart_tx(
	Clk,
	Rst_n,
	baud_set,
	data_byte,
	send_en,
	
	rs232_tx,
	Tx_Done,
	uart_state //*******
);
	input    Clk;
	input    Rst_n;
	input  [2:0]  baud_set;
	input   [7:0] data_byte;//******[9:0] ---> [7:0]
	input    send_en;
	
	output reg [7:0] rs232_tx;   //******[7:0]
	output reg     Tx_Done;
	output reg     uart_state; //*******
	
	reg [16:0] div_cnt;//分频计数器
	reg bps_clk;//分频计数时钟
	reg [15:0] bps_DR;  //分频计算最大值
	reg [3:0] bps_cnt;//波特率计算时钟
	
	reg [7:0] r_data_byte;//寄存器
	
	localparam START_BIT = 1'b0; 
	localparam STOP_BIT = 1'b1; 
	
	//uart_state
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		uart_state <= 1'b0;
	else if(send_en)
		uart_state <= 1'b1;
	else if(Tx_Done)
		uart_state <= 1'b0;
	else
		uart_state <= uart_state;
	
	//r_data_byte寄存器
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		r_data_byte <= 8'd0;
	else if(send_en)
		r_data_byte <= data_byte;
	else
		r_data_byte <= r_data_byte;
	
	//DR_LUT
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		bps_DR <= 16'd5207;
	else begin
		case(baud_set)
			0:bps_DR <= 16'd5207; //9600
			1:bps_DR <= 16'd2603;
			2:bps_DR <= 16'd1301;
			3:bps_DR <= 16'd867;
			4:bps_DR <= 16'd433;
			default:bps_DR <= 16'd5207;
		endcase
	end
	
	//分频计数器
	always@(posedge Clk or negedge Rst_n) 
	begin
		if(!Rst_n) 
			div_cnt <= 16'd0;
		else if(uart_state)begin  //满足大条件使能时,en_cnt可以用uart_state替换
			if(div_cnt ==  bps_DR) //计数到最大值 
				div_cnt <= 16'd0;
			else
				div_cnt <= div_cnt + 1'd1;
		 end
		 else
		 div_cnt <= 16'd0; //不满足使能时就不计数
	end
	
	//bps_clk;
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		bps_clk <= 1'b0;
	else if(div_cnt == 16'd1)  //计算到1就产生高脉冲
		bps_clk <= 1'b1;
	else
		bps_clk <= 1'b0;  //bps_clk + 1'b1 ---> 1'b0
	
	//bps_cnt
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		bps_cnt <= 4'b0;
	else if(Tx_Done)   //clr等于Tx_Done
		bps_cnt <= 4'b0;
	else if(bps_clk)
		bps_cnt <= bps_cnt + 1'b1;
	else
		bps_cnt <= bps_cnt;
		
	//Tx_Done
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		Tx_Done <= 1'b0;
	else if(bps_cnt == 4'd11)
		Tx_Done <= 1'b1;
	else
		Tx_Done <= 1'b0;
		
	//十选一多路器
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)
		rs232_tx <=1'b1;
	else begin
		case(bps_cnt)
			 0:rs232_tx <= 1'b1; //高电平输出
			 1:rs232_tx <= START_BIT;
			 2:rs232_tx <= r_data_byte[0];
			 3:rs232_tx <= r_data_byte[1];
			 4:rs232_tx <= r_data_byte[2];
			 5:rs232_tx <= r_data_byte[3];
			 6:rs232_tx <= r_data_byte[4];
			 7:rs232_tx <= r_data_byte[5];
			 8:rs232_tx <= r_data_byte[6]; 
			 9:rs232_tx <= r_data_byte[7];
		   10:rs232_tx <= STOP_BIT;
			default:rs232_tx <=1'b1;
		endcase
	end
	
endmodule