最近看关于FPGA的结构,发现LUT实际上是可以使用原语或者原理图中添加symbol调用。symbol information中有关于这个元件的例化原语。
----------------------------------------------------------------------------------------------------------------------
---------------VHDL Instantiation Template
Unless they already exist, copy thefollowing two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT4_L: 4-input Look-Up Table with localoutput
-- Xilinx HDL Libraries Guide, version 10.1
LUT4_L_inst : LUT4_L
generic map (
INIT => X"0000")
port map (
LO => LO, -- LUT local output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3 -- LUT input
);
-- End of LUT4_L_inst instantiation
-------------------------------------