module clk_div //任意奇数分频,其分频率由N决定
(clk_out,reset,clk_in);
output clk_out;
input reset,clk_in;
reg clk_out;
reg clk1,clk2;
reg [2:0] counter;
parameter N=3;//N=3表示三分频
always @ (posedge clk_in)
if(!reset)
begin
clk1<=0;
counter<=0;
end
else
begin
counter<=counter+1'b1;
if(counter==(N-1)/2)
clk1<=~clk1;
else if(counter==(N-1))
begin
clk1<=~clk1;
counter<=0;
end
end
always @ (negedge clk_in)
begin
if(!reset)
clk2<=0;
else
clk2<=clk1;
end
always @ (clk1 or clk2)
begin
clk_out<=clk1 | clk2;
end
endmodule
(clk_out,reset,clk_in);
output clk_out;
input reset,clk_in;
reg clk_out;
reg clk1,clk2;
reg [2:0] counter;
parameter N=3;//N=3表示三分频
always @ (posedge clk_in)
if(!reset)
begin
clk1<=0;
counter<=0;
end
else
begin
counter<=counter+1'b1;
if(counter==(N-1)/2)
clk1<=~clk1;
else if(counter==(N-1))
begin
clk1<=~clk1;
counter<=0;
end
end
always @ (negedge clk_in)
begin
if(!reset)
clk2<=0;
else
clk2<=clk1;
end
always @ (clk1 or clk2)
begin
clk_out<=clk1 | clk2;
end
endmodule