1.4 Nios II顶层源程序
`timescale 1 ps / 1 ps
module audio_nios (
input wire clk_clk, // clk.clk
input wire [31:0] din32_external_connection_export, // din32_external_connection.export
input wire [3:0] key_external_connection_export, // key_external_connection.export
output wire [9:0] pio_0_external_connection_export, // pio_0_external_connection.export
output wire pll_locked_export, // pll_locked.export
output wire pll_outclk3_clk, // pll_outclk3.clk
output wire pll_sdam_clk, // pll_sdam.clk
input wire rd_empt_external_connection_export, // rd_empt_external_connection.export
output wire rd_rqt_external_connection_export, // rd_rqt_external_connection.export
input wire reset_reset_n, // reset.reset_n
output wire [12:0] sdram_wire_addr, // sdram_wire.addr
output wire [1:0] sdram_wire_ba, // .ba
output wire sdram_wire_cas_n, // .cas_n
output wire sdram_wire_cke, // .cke
output wire sdram_wire_cs_n, // .cs_n
inout wire [15:0] sdram_wire_dq, // .dq
output wire [1:0] sdram_wire_dqm, // .dqm
output wire sdram_wire_ras_n, // .ras_n
output wire sdram_wire_we_n, // .we_n
output wire [47:0] seg7_conduit_end_export, // seg7_conduit_end.export
input wire [9:0] sw_external_connection_export, // sw_external_connection.export
input wire wr_full_external_connection_export // wr_full_external_connection.export
);
wire pll_outclk0_clk; // pll:outclk_0 -> [cpu:clk, cpu_peripheral_bridge:s0_clk, irq_mapper:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, irq_synchronizer_002:sender_clk, jtag_uart:clk, mm_interconnect_0:pll_outclk0_clk, onchip_memory2:clk, rst_controller:clk, rst_controller_002:clk, sdram:clk, sysid_qsys:clock, timer:clk]
wire pll_outclk2_clk; // pll:outclk_2 -> [cpu_peripheral_bridge:m0_clk, din32:clk, irq_synchronizer:receiver_clk, irq_synchronizer_001:receiver_clk, irq_synchronizer_002:receiver_clk, key:clk, mm_interconnect_1:pll_outclk2_clk, pio_led:clk, rd_empt:clk, rd_rqt:clk, rst_controller_001:clk, seg7:s_clk, sw:clk, wr_full:clk]
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [26:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire cpu_data_master_readdatavalid; // mm_interconnect_0:cpu_data_master_readdatavalid -> cpu:d_readdatavalid
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [26:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire cpu_instruction_master_readdatavalid; // mm_interconnect_0:cpu_instruction_master_readdatavalid -> cpu:i_readdatavalid
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_0_sysid_qsys_control_slave_address; // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata; // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata
wire mm_interconnect_0_cpu_debug_mem_slave_waitrequest; // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest
wire mm_interconnect_0_cpu_debug_mem_slave_debugaccess; // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_cpu_debug_mem_slave_address; // mm_interconnect_0:cpu_debug_mem_slave_address -> cpu:debug_mem_slave_address
wire mm_interconnect_0_cpu_debug_mem_slave_read; // mm_interconnect_0:cpu_debug_mem_slave_read -> cpu:debug_mem_slave_read
wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
wire [31:0] mm_interconnect_0_cpu_peripheral_bridge_s0_readdata; // cpu_peripheral_bridge:s0_readdata -> mm_interconnect_0:cpu_peripheral_bridge_s0_readdata
wire mm_interconnect_0_cpu_peripheral_bridge_s0_waitrequest; // cpu_peripheral_bridge:s0_waitrequest -> mm_interconnect_0:cpu_peripheral_bridge_s0_waitrequest
wire mm_interconnect_0_cpu_peripheral_bridge_s0_debugaccess; // mm_interconnect_0:cpu_peripheral_bridge_s0_debugaccess -> cpu_peripheral_bridge:s0_debugaccess
wire [8:0] mm_interconnect_0_cpu_peripheral_bridge_s0_address; // mm_interconnect_0:cpu_peripheral_bridge_s0_address -> cpu_peripheral_bridge:s0_address
wire mm_interconnect_0_cpu_peripheral_bridge_s0_read; // mm_interconnect_0:cpu_peripheral_bridge_s0_read -> cpu_peripheral_bridge:s0_read
wire [3:0] mm_interconnect_0_cpu_peripheral_bridge_s0_byteenable; // mm_interconnect_0:cpu_peripheral_bridge_s0_byteenable -> cpu_peripheral_bridge:s0_byteenable
wire mm_interconnect_0_cpu_peripheral_bridge_s0_readdatavalid; // cpu_peripheral_bridge:s0_readdatavalid -> mm_interconnect_0:cpu_peripheral_bridge_s0_readdatavalid
wire mm_interconnect_0_cpu_peripheral_bridge_s0_write; // mm_interconnect_0:cpu_peripheral_bridge_s0_write -> cpu_peripheral_bridge:s0_write wire [31:0] mm_interconnect_0_cpu_peripheral_bridge_s0_writedata; // mm_interconnect_0:cpu_peripheral_bridge_s0_writedata -> cpu_peripheral_bridge:s0_writedata wire [0:0] mm_interconnect_0_cpu_peripheral_bridge_s0_burstcount; // mm_interconnect_0:cpu_peripheral_bridge_s0_burstcount -> cpu_peripheral_bridge:s0_burstcount wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs wire [15:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest wire [24:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n wire [1:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n wire [15:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data wire mm_interconnect_0_onchip_memory2_s1_chipselect; // mm_interconnect_0:onchip_memory2_s1_chipselect -> onchip_memory2:chipselect wire [31:0] mm_interconnect_0_onchip_memory2_s1_readdata; // onchip_memory2:readdata -> mm_interconnect_0:onchip_memory2_s1_readdata wire [16:0] mm_interconnect_0_onchip_memory2_s1_address; // mm_interconnect_0:onchip_memory2_s1_address -> onchip_memory2:address wire [3:0] mm_interconnect_0_onchip_memory2_s1_byteenable; // mm_interconnect_0:onchip_memory2_s1_byteenable -> onchip_memory2:byteenable wire mm_interconnect_0_onchip_memory2_s1_write; // mm_interconnect_0:onchip_memory2_s1_write -> onchip_memory2:write wire [31:0] mm_interconnect_0_onchip_memory2_s1_writedata; // mm_interconnect_0:onchip_memory2_s1_writedata -> onchip_memory2:writedata wire mm_interconnect_0_onchip_memory2_s1_clken; // mm_interconnect_0:onchip_memory2_s1_clken -> onchip_memory2:clken wire mm_interconnect_0_timer_s1_chipselect; // mm_interconnect_0:timer_s1_chipselect -> timer:chipselect wire [15:0] mm_interconnect_0_timer_s1_readdata; // timer:readdata -> mm_interconnect_0:timer_s1_readdata wire [2:0] mm_interconnect_0_timer_s1_address; // mm_interconnect_0:timer_s1_address -> timer:address wire mm_interconnect_0_timer_s1_write; // mm_interconnect_0:timer_s1_write -> timer:write_n wire [15:0] mm_interconnect_0_timer_s1_writedata; // mm_interconnect_0:timer_s1_writedata -> timer:writedata wire cpu_peripheral_bridge_m0_waitrequest; // mm_interconnect_1:cpu_peripheral_bridge_m0_waitrequest -> cpu_peripheral_bridge:m0_waitrequest wire [31:0] cpu_peripheral_bridge_m0_readdata; // mm_interconnect_1:cpu_peripheral_bridge_m0_readdata -> cpu_peripheral_bridge:m0_readdata wire cpu_peripheral_bridge_m0_debugaccess; // cpu_peripheral_bridge:m0_debugaccess -> mm_interconnect_1:cpu_peripheral_bridge_m0_debugaccess wire [8:0] cpu_peripheral_bridge_m0_address; // cpu_peripheral_bridge:m0_address -> mm_interconnect_1:cpu_peripheral_bridge_m0_address wire cpu_peripheral_bridge_m0_read; // cpu_peripheral_bridge:m0_read -> mm_interconnect_1:cpu_peripheral_bridge_m0_read wire [3:0] cpu_peripheral_bridge_m0_byteenable; // cpu_peripheral_bridge:m0_byteenable -> mm_interconnect_1:cpu_peripheral_bridge_m0_byteenable wire cpu_peripheral_bridge_m0_readdatavalid; // mm_interconnect_1:cpu_peripheral_bridge_m0_readdatavalid -> cpu_peripheral_bridge:m0_readdatavalid wire [31:0] cpu_peripheral_bridge_m0_writedata; // cpu_peripheral_bridge:m0_writedata -> mm_interconnect_1:cpu_peripheral_bridge_m0_writedata wire cpu_peripheral_bridge_m0_write; // cpu_peripheral_bridge:m0_write -> mm_interconnect_1:cpu_peripheral_bridge_m0_write wire [0:0] cpu_peripheral_bridge_m0_burstcount; // cpu_peripheral_bridge:m0_burstcount -> mm_interconnect_1:cpu_peripheral_bridge_m0_burstcount wire [7:0] mm_interconnect_1_seg7_avalon_slave_readdata; // seg7:s_readdata -> mm_interconnect_1:seg7_avalon_slave_readdata wire [2:0] mm_interconnect_1_seg7_avalon_slave_address; // mm_interconnect_1:seg7_avalon_slave_address -> seg7:s_address wire mm_interconnect_1_seg7_avalon_slave_read; // mm_interconnect_1:seg7_avalon_slave_read -> seg7:s_read wire mm_interconnect_1_seg7_avalon_slave_write; // mm_interconnect_1:seg7_avalon_slave_write -> seg7:s_write wire [7:0] mm_interconnect_1_seg7_avalon_slave_writedata; // mm_interconnect_1:seg7_avalon_slave_writedata -> seg7:s_writedata wire mm_interconnect_1_key_s1_chipselect; // mm_interconnect_1:key_s1_chipselect -> key:chipselect wire [31:0] mm_interconnect_1_key_s1_readdata; // key:readdata -> mm_interconnect_1:key_s1_readdata wire [1:0] mm_interconnect_1_key_s1_address; // mm_interconnect_1:key_s1_address -> key:address wire mm_interconnect_1_key_s1_write; // mm_interconnect_1:key_s1_write -> key:write_n wire [31:0] mm_interconnect_1_key_s1_writedata; // mm_interconnect_1:key_s1_writedata -> key:writedata wire mm_interconnect_1_pio_led_s1_chipselect; // mm_interconnect_1:pio_led_s1_chipselect -> pio_led:chipselect wire [31:0] mm_interconnect_1_pio_led_s1_readdata; // pio_led:readdata -> mm_interconnect_1:pio_led_s1_readdata wire [1:0] mm_interconnect_1_pio_led_s1_address; // mm_interconnect_1:pio_led_s1_address -> pio_led:address wire mm_interconnect_1_pio_led_s1_write; // mm_interconnect_1:pio_led_s1_write -> pio_led:write_n wire [31:0] mm_interconnect_1_pio_led_s1_writedata; // mm_interconnect_1:pio_led_s1_writedata -> pio_led:writedata wire mm_interconnect_1_sw_s1_chipselect; // mm_interconnect_1:sw_s1_chipselect -> sw:chipselect wire [31:0] mm_interconnect_1_sw_s1_readdata; // sw:readdata -> mm_interconnect_1:sw_s1_readdata wire [1:0] mm_interconnect_1_sw_s1_address; // mm_interconnect_1:sw_s1_address -> sw:address wire mm_interconnect_1_sw_s1_write; // mm_interconnect_1:sw_s1_write -> sw:write_n wire [31:0] mm_interconnect_1_sw_s1_writedata; // mm_interconnect_1:sw_s1_writedata -> sw:writedata wire [31:0] mm_interconnect_1_din32_s1_readdata; // din32:readdata -> mm_interconnect_1:din32_s1_readdata wire [1:0] mm_interconnect_1_din32_s1_address; // mm_interconnect_1:din32_s1_address -> din32:address wire mm_interconnect_1_wr_full_s1_chipselect; // mm_interconnect_1:wr_full_s1_chipselect -> wr_full:chipselect wire [31:0] mm_interconnect_1_wr_full_s1_readdata; // wr_full:readdata -> mm_interconnect_1:wr_full_s1_readdata wire [1:0] mm_interconnect_1_wr_full_s1_address; // mm_interconnect_1:wr_full_s1_address -> wr_full:address wire mm_interconnect_1_wr_full_s1_write; // mm_interconnect_1:wr_full_s1_write -> wr_full:write_n wire [31:0] mm_interconnect_1_wr_full_s1_writedata; // mm_interconnect_1:wr_full_s1_writedata -> wr_full:writedata wire mm_interconnect_1_rd_rqt_s1_chipselect; // mm_interconnect_1:rd_rqt_s1_chipselect -> rd_rqt:chipselect wire [31:0] mm_interconnect_1_rd_rqt_s1_readdata; // rd_rqt:readdata -> mm_interconnect_1:rd_rqt_s1_readdata wire [1:0] mm_interconnect_1_rd_rqt_s1_address; // mm_interconnect_1:rd_rqt_s1_address -> rd_rqt:address wire mm_interconnect_1_rd_rqt_s1_write; // mm_interconnect_1:rd_rqt_s1_write -> rd_rqt:write_n wire [31:0] mm_interconnect_1_rd_rqt_s1_writedata; // mm_interconnect_1:rd_rqt_s1_writedata -> rd_rqt:writedata wire [31:0] mm_interconnect_1_rd_empt_s1_readdata; // rd_empt:readdata -> mm_interconnect_1:rd_empt_s1_readdata wire [1:0] mm_interconnect_1_rd_empt_s1_address; // mm_interconnect_1:rd_empt_s1_address -> rd_empt:address wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq wire irq_mapper_receiver3_irq; // timer:irq -> irq_mapper:receiver3_irq wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq wire irq_mapper_receiver1_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq wire [0:0] irq_synchronizer_receiver_irq; // key:irq -> irq_synchronizer:receiver_irq wire irq_mapper_receiver2_irq; // irq_synchronizer_001:sender_irq -> irq_mapper:receiver2_irq wire [0:0] irq_synchronizer_001_receiver_irq; // sw:irq -> irq_synchronizer_001:receiver_irq wire irq_mapper_receiver4_irq; // irq_synchronizer_002:sender_irq -> irq_mapper:receiver4_irq wire [0:0] irq_synchronizer_002_receiver_irq; // wr_full:irq -> irq_synchronizer_002:receiver_irq wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset] wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, rst_translator:reset_req_in] wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1 wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [cpu_peripheral_bridge:m0_reset, din32:reset_n, irq_synchronizer:receiver_reset, irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, key:reset_n, mm_interconnect_1:cpu_peripheral_bridge_m0_reset_reset_bridge_in_reset_reset, pio_led:reset_n, rd_empt:reset_n, rd_rqt:reset_n, seg7:s_reset, sw:reset_n, wr_full:reset_n] wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [cpu_peripheral_bridge:s0_reset, jtag_uart:rst_n, mm_interconnect_0:jtag_uart_reset_reset_bridge_in_reset_reset, onchip_memory2:reset, rst_translator_001:in_reset, sdram:reset_n, sysid_qsys:reset_n, timer:reset_n] wire rst_controller_002_reset_out_reset_req; // rst_controller_002:reset_req -> [onchip_memory2:reset_req, rst_translator_001:reset_req_in] audio_nios_cpu cpu ( .clk (pll_outclk0_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .reset_req (rst_controller_reset_out_reset_req), // .reset_req .d_address (cpu_data_master_address), // data_master.address .d_byteenable (cpu_data_master_byteenable), // .byteenable .d_read (cpu_data_master_read), // .read .d_readdata (cpu_data_master_readdata), // .readdata .d_waitrequest (cpu_data_master_waitrequest), // .waitrequest .d_write (cpu_data_master_write), // .write .d_writedata (cpu_data_master_writedata), // .writedata .d_readdatavalid (cpu_data_master_readdatavalid), // .readdatavalid .debug_mem_slave_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess .i_address (cpu_instruction_master_address), // instruction_master.address .i_read (cpu_instruction_master_read), // .read .i_readdata (cpu_instruction_master_readdata), // .readdata .i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest .i_readdatavalid (cpu_instruction_master_readdatavalid), // .readdatavalid .irq (cpu_irq_irq), // irq.irq
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