ep240--all

openlight

module openlight(sh,q,clk);
		input sh;
		input clk;
		output q;
		
		reg q;
		reg[10:0] counter;
		
		always@(posedge clk ) //sh=550us period
			begin
				if(sh==1'b0)
					begin
						counter<=11'b0;
						q<=1'b0;
					end
				else
					begin
						counter<=counter+1'b1;  //640ns
						if(counter<11'd500)
							begin
								q<=1'b0;
							end
						else if(counter<11'd858)           //550/0.64=860count 
							begin
								q<=1'b1;
							end
						else
							begin
								q<=1'b0;
								counter<=11'b0;
							end
					end
			end
		
endmodule
		

adclk

module ADCLK(clk,q,en); //en is fai2 
	input clk;// 50m
	input en;
	output q;
	reg q;
	reg[3:0] counter;
	always@(posedge clk)
		begin
			if(en==1'b1)
				begin
					q<=1'b0;
					counter<=4'b0;
				end
			else 
				begin
					if(counter<4'd2)
						begin
							counter<=counter+1'b1;
							q<=1'b1;
						end
					else
						begin
							q<=1'b0;
							counter<=counter;
						end					
				end
		end
endmodule

autoint

module autoint(fai1en,fai1,q);
		input fai1;
		input fai1en;
		output q;
		reg q;
		reg[11:0] counter;
		
		always@(posedge fai1 or negedge fai1en)
			begin
				if(fai1en==1'b0)
					begin
						counter<=12'b0;
						
					end
				else
					begin
						counter<=counter+1'b1;
						if(counter<12'd2150)
							begin
								
								q<=1'b0;
							end
						else if((counter>12'd2149) && (counter<12'd2350) ) //200*160ns=32us time for stm32
							begin
								q<=1'b1;  //          auto  clear   ,when finsh,q=1,and wait for 2us
							end
						else
							begin
								q<=1'b0;
								counter<=12'b0;
							end
					end
			end



endmodule

statusccd

module statusccd(clk,sh,fai1,fai1en,light,busy);
	input clk; // clk50m 
	//output[7:0] q; // output led 
	output sh;
	output light;
	output fai1;
	output fai1en;
	output busy;
	reg busy;
	reg light;
	reg sh;
	reg fai1;
	reg fai1en;
	//reg[7:0] q;
	reg[15:0] counter;
	reg[3:0] status;
	always@(posedge clk)  //20ns
		begin
			
			if(counter<16'd27501)   //max period about 550 us 
				begin
					
					counter<=counter+1'b1;
					
				end
			else                    // loop
				begin
					counter<=16'd0;
				end
			//*******************************************
			if((counter>16'd1) && (counter<16'd7))// 120ns for reset all singal
				begin
					status<=4'b0001;
					
				end
			else if((counter>16'd6) && (counter<16'd17)) // 100 ns for fai1 before SH
				begin
					status<=4'b0010;
				end
			else if((counter>16'd16) && (counter<16'd85)) // 1300 ns for  SH is high 66*20=1320ns
				begin
					status<=4'b0011;
				end
			else if((counter>16'd84) && (counter<16'd107)) // 520 ns for  fai1 goes to low before SH
				begin
					status<=4'b0100;
					
				end
			else if((counter>16'd106) && (counter<16'd17307)) // 344us ns for  SH is low to shift data to OS
				begin                                          // 216us for led light
					status<=4'b0101;
					
				end
			else if((counter>16'd17306) && (counter<16'd28105)) // 216us for low ,waiting for next loop
				begin
					status<=4'b0110;  //ide time 
					
					
				end
			else
				begin
					status<=4'b0000;
				end
		end
//--------------------------------------------------------------------------------------------
		always@(posedge clk)
			begin
				case(status[3:0])
				4'b0000:begin
							sh<=1'b0;
							fai1<=1'b0;
							fai1en<=1'b0;
							light<=1'b0;//   turn off light
							busy<=1'b0;
						end
				4'b0001:begin
							sh<=1'b0;
							fai1<=1'b0;
							fai1en<=1'b0;
							//light<=1'b0;//   turn off light
							//busy<=1'b0;
						end
				4'b0010:begin
							fai1<=1'b1;
							fai1en<=1'b1;
						end
				4'b0011:begin
							sh<=1'b1;
							fai1<=1'b1;
							fai1en<=1'b1;
						end
				4'b0100:begin
							sh<=1'b0;
							fai1<=1'b1;
							fai1en<=1'b1;
						end
				4'b0101:begin
							light<=1'b1;//   turn on light
							fai1<=1'b0;
							fai1en<=1'b1;
						end
				4'b0110:begin
							sh<=1'b0;
							fai1<=1'b0;
							fai1en<=1'b1;
							busy<=1'b1;
							light<=1'b0;//   turn off light
						end
				default:begin
							sh<=1'b0;
							fai1<=1'b0;
							fai1en<=1'b0;
							busy<=1'b0;
							light<=1'b0;//   turn off light
						end
				endcase

			end
endmodule

eom

module eom(clk,d77,ccdlight,meastime);
	input clk;//clk50m
	input d77;// ad msb d7
	input ccdlight; //light time 
	output meastime;// test time 
	reg meastime; //reg
	reg[15:0] cnt; //count time
	
	always@(posedge clk)
	begin
	if(ccdlight==1'b0)
		begin
			cnt<=16'b0;
			meastime<=1'b0;
		end
	else if((cnt>10'd270)&&(cnt<16'd16400)) 
		begin
			meastime<=1'b1;
		end
	else
		begin
			meastime<=1'b0;
			cnt<=cnt+1'b1;
	    end
	    
	 end

endmodule

RS

module RS(clk,q,en); //en is fai2 
	input clk;// 50m
	input en;
	output q;
	reg q;
	reg[1:0] counter;
	always@(posedge clk)
		begin
			if(en==1'b0)
				begin
					q<=1'b0;
					counter<=2'b0;
				end
			else
				begin
					counter<=counter+1'b1;
					if(counter<2'd1)
						begin
							
							q<=1'b0;
						end
					else if( counter<2'd3)
						begin
							
							q<=1'b1;
						end
					else
						begin
							q<=1'b0;
						end
					
			
				end
		end

endmodule

CP

module CP(clk,q,en); //en is fai2 
	input clk;// 50m
	input en;
	output q;
	reg q;
	reg[1:0] counter;
	always@(posedge clk)
		begin
			if(en==1'b0)
				begin
					q<=1'b0;
					counter<=2'b0;
				end
			else
				begin
					counter<=counter+1'b1;
					if(counter<2'd2)
						begin
							
							q<=1'b0;
						end
					else if(counter<2'd3)
						begin
							q<=1'b1;
						end
					else
						begin
							
							q<=1'b0;
						end
					
			
				end
		end

endmodule