S32K312使用ITCM向FLASH代码区写入数据

使用C40_IP的系列方法向FLASH代码区写入数据时，程序会卡死在读取写操作的状态C40_Ip_MainInterfaceWriteStatus()这个方法中。本文主要介绍S32K312通过ITCM的方式，通过C40_IP的方法向FLASH代码区成功写入数据的方法和步骤。

首先，验证一下C40_IP写入FLASH代码区时行不通的。通过官方例程的代码C40_IP_Example_S32K312，修改了2个参数，使得程序擦除和写入FLASH代码区：

修改完成后进行代码调试，找到程序卡死的地方

接下来描述，使用ITCM的方式对FLASH代码区进行擦除和写入，程序正常运行且结果达到预期的步骤：

1、ITCM的如何使用，参考《S32K312 ITCM代码使用示例》这篇文章。

几个注意事项

1.1、linker_flash_s32k312.ld这个文件需要修改一下

.ld文件的代码段

/*==================================================================================================
*   Project              : RTD AUTOSAR 4.4
*   Platform             : CORTEXM
*   Peripheral           : 
*   Dependencies         : none
*
*   Autosar Version      : 4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 2.0.1
*   Build Version        : S32K3_RTD_2_0_1_D2207_ASR_REL_4_4_REV_0000_20220707
*
*   (c) Copyright 2020 - 2022 NXP Semiconductors
*   All Rights Reserved.
*
*   NXP Confidential. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/
/*
* GCC Linker Command File:
* 0x00400000    0x001F3FFF  2047999 Program Flash (last 64K sBAF)
* 0x10000000    0x1003FFFF  262144  Data Flash (last 32K HSE_NVM)
* 0x20400000    0x20408000  32768   Standby RAM_0 (32K)
* 0x20400000    0x20417FFF  98304   SRAM_0 (96KB)
* Last 48 KB of SRAM_1 reserved by HSE Firmware
* Last 176 KB of CODE_FLASH_3 reserved by HSE Firmware
* Last 128 KB of DATA_FLASH reserved by HSE Firmware (not supported in this linker file)
*/
HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x00002000;

ENTRY(Reset_Handler)

MEMORY 
{         
    int_flash               : ORIGIN = 0x00400000, LENGTH = 0x001D4000    /* 2048K - 176K (sBAF + HSE)*/
    int_itcm                : ORIGIN = 0x00000000, LENGTH = 0x00008000    /* 32K */
    int_dtcm                : ORIGIN = 0x20000000, LENGTH = 0x00010000    /* 64K */
    int_sram                : ORIGIN = 0x20400000, LENGTH = 0x00006F00    /* 27 KB */
    int_sram_fls_rsv        : ORIGIN = 0x20406F00, LENGTH = 0x00000100    
    int_sram_stack_c0       : ORIGIN = 0x20407000, LENGTH = 0x00001000    
    int_sram_no_cacheable   : ORIGIN = 0x20408000, LENGTH = 0x00007F00    /* 32kb , needs to include int_results  */
    int_sram_results        : ORIGIN = 0x2040FF00, LENGTH = 0x00000100    
    int_sram_shareable      : ORIGIN = 0x20410000, LENGTH = 0x00008000    /* 32KB */
    ram_rsvd2               : ORIGIN = 0x20418000, LENGTH = 0             /* End of SRAM */
}


SECTIONS
{
    
    .flash :
    {
    	KEEP(*(.boot_header))
        . = ALIGN(4096);
        __text_start = .;
        __interrupts_rom_start = .;
        KEEP(*(.intc_vector))    
        . = ALIGN(4);
        __interrupts_rom_end = .;
        KEEP(*(.core_loop)) 
        . = ALIGN(4);
        *(.startup) 
        . = ALIGN(4);
        *(.systeminit) 
        . = ALIGN(4);
        *(.text.startup) 
        . = ALIGN(4);
        *(EXCLUDE_FILE (*C40_Ip.o) .text)
        *(.text*) 
        . = ALIGN(4);
        *(EXCLUDE_FILE (*C40_Ip.o) .mcal_text) 
        . = ALIGN(4);
        *(.acmcu_code_rom)
        . = ALIGN(4);
        __acfls_code_rom_start = .;
        *(.acfls_code_rom) 
        . = ALIGN(4);
        __acfls_code_rom_end = .;
        KEEP(*(.init))
        . = ALIGN(4);
        KEEP(*(.fini)) 
         
        . = ALIGN(4);
        *(.rodata)  
        *(.rodata*)  
        . = ALIGN(4);
        *(.mcal_const_cfg)  
        . = ALIGN(4);
        *(.mcal_const)  
        . = ALIGN(4);
        __init_table = .;
        KEEP(*(.init_table))  
        . = ALIGN(4);
        __zero_table = .;
        KEEP(*(.zero_table))
    } > int_flash

    . = ALIGN(4);
    __text_end = .;
    __sram_data_rom = __text_end;
    
    .sram_data : AT(__sram_data_rom)
    {
        . = ALIGN(4);
        __sram_data_begin__ = .;
        . = ALIGN(4);
        *(.ramcode)    
        . = ALIGN(4);
        *(.data)  
        *(.data*)
        . = ALIGN(4);
        *(.mcal_data)
        . = ALIGN(4);
        __sram_data_end__ = .;
    } > int_sram

    __sram_data_rom_end = __sram_data_rom + (__sram_data_end__ - __sram_data_begin__);
    .sram_bss (NOLOAD) :
    {
        . = ALIGN(16);
        __sram_bss_start = .;
        *(.bss)
        *(.bss*)
        . = ALIGN(16);
        *(.mcal_bss)
        . = ALIGN(4);
        __sram_bss_end = .;
    } > int_sram
    /* heap section */        
    .heap (NOLOAD):
    {
    	. += ALIGN(4);
	    _end = .;
	    end = .;
        _heap_start = .;
        . += HEAP_SIZE;
        _heap_end = .;
    } > int_sram
    
    
    .acfls_code_ram :
    {
        acfls_code_ram_start  = .;
        *(.acfls_code_ram)
        acfls_code_ram_stop   = .;
    } > int_sram_fls_rsv

    __non_cacheable_data_rom = __sram_data_rom_end;

    .non_cacheable_data : AT(__non_cacheable_data_rom)
    {
        . = ALIGN(4);
        __non_cacheable_data_start__ = .;
        . = ALIGN(4096);
        __interrupts_ram_start = .;
        . += __interrupts_rom_end - __interrupts_rom_start;    
        . = ALIGN(4);
        __interrupts_ram_end = .;
        *(.mcal_data_no_cacheable)        
        . = ALIGN(4);
        *(.mcal_const_no_cacheable)      
        . = ALIGN(4);
        HSE_LOOP_ADDR = .;
        LONG(0x0);
        __non_cacheable_data_end__ = .;  
    } > int_sram_no_cacheable

	int_results (NOLOAD):
	{
		. = ALIGN(4);
        KEEP(*(.int_results))  
        . += 0x100;
	} > int_sram_results
    
    __non_cacheable_data_rom_end = __non_cacheable_data_rom + (__non_cacheable_data_end__ - __non_cacheable_data_start__);

    .non_cacheable_bss (NOLOAD) :
    {  
        . = ALIGN(16);
        __non_cacheable_bss_start = .;
        *(.mcal_bss_no_cacheable)      
        . = ALIGN(4);
        __non_cacheable_bss_end = .;       
    } > int_sram_no_cacheable
    
    __shareable_data_rom = __non_cacheable_data_rom_end;

    .shareable_data : AT(__shareable_data_rom)
    {
        . = ALIGN(4);
        __shareable_data_start__ = .;
        KEEP(*(.mcal_shared_data)) 
        . = ALIGN(4);
        __shareable_data_end__ = .;  
    } > int_sram_shareable

    __shareable_data_rom_end = __shareable_data_rom + (__shareable_data_end__ - __shareable_data_start__);

    .shareable_bss (NOLOAD) :
    {  
        . = ALIGN(16);
        __shareable_bss_start = .;
        *(.mcal_shared_bss)      
        . = ALIGN(4);
        __shareable_bss_end = .;       
    } > int_sram_shareable
    
    __itcm0_code_rom = __shareable_data_rom_end;

    .itcm0_code : AT(__itcm0_code_rom)
    {
        . = ALIGN(4);
        __itcm0_code_start__ = .;
        KEEP(*(.itcm0_code)) 
        KEEP(*C40_Ip.o(.mcal_text*))
        KEEP(*C40_Ip.o(.text*))
        . = ALIGN(4);
        __itcm0_code_end__ = .;  
    } > int_itcm

    __itcm0_code_rom_end = __itcm0_code_rom + (__itcm0_code_end__ - __itcm0_code_start__);
    
    __dtcm0_data_rom = __itcm0_code_rom_end;

    .dtcm0_data : AT(__dtcm0_data_rom)
    {
        . = ALIGN(4);
        __dtcm0_data_start__ = .;
        KEEP(*(.dtcm0_data)) 
        . = ALIGN(4);
        __dtcm0_data_end__ = .;  
    } > int_dtcm

    __dtcm0_data_rom_end = __dtcm0_data_rom + (__dtcm0_data_end__ - __dtcm0_data_start__);

    __Stack_end_c0           = ORIGIN(int_sram_stack_c0);
    __Stack_start_c0         = ORIGIN(int_sram_stack_c0) + LENGTH(int_sram_stack_c0);
    __Stack_end_c1           = 0;
    __Stack_start_c1         = 0;

    __INT_SRAM_START         = ORIGIN(int_sram);
    __INT_SRAM_END           = ORIGIN(ram_rsvd2);
    
    __INT_ITCM_START         = ORIGIN(int_itcm);
    __INT_ITCM_END           = ORIGIN(int_itcm) + LENGTH(int_itcm);
    
    __INT_DTCM_START         = ORIGIN(int_dtcm);
    __INT_DTCM_END           = ORIGIN(int_dtcm) + LENGTH(int_dtcm);
    
    __RAM_SHAREABLE_START    = ORIGIN(int_sram_shareable);
    __RAM_SHAREABLE_END      = ORIGIN(ram_rsvd2)-1;
    __RAM_SHAREABLE_SIZE     = 0xF;
    __ROM_SHAREABLE_START    = __shareable_data_rom;
    __ROM_SHAREABLE_END      = __shareable_data_rom_end;
    __RAM_NO_CACHEABLE_START = ORIGIN(int_sram_no_cacheable);
    __RAM_NO_CACHEABLE_END   = ORIGIN(int_sram_shareable)-1;
    __RAM_NO_CACHEABLE_SIZE  = 0xF;  /* 32kbyte in power of 2 */
    __ROM_NO_CACHEABLE_START = __non_cacheable_data_rom;
    __ROM_NO_CACHEABLE_END   = __non_cacheable_data_rom_end;
    __RAM_CACHEABLE_START    = ORIGIN(int_sram);
    __RAM_CACHEABLE_END      = ORIGIN(int_sram_no_cacheable)-1;
    __RAM_CACHEABLE_SIZE     = 0xF;  /* 32kbyte in power of 2 */
    __ROM_CACHEABLE_START    = __sram_data_rom;
    __ROM_CACHEABLE_END      = __sram_data_rom_end;
    __ROM_CODE_START         = ORIGIN(int_flash);
    __ROM_DATA_START         = 0x10000000;
    __RAM_ITCM0_CODE_START   = __itcm0_code_start__;
    __ROM_ITCM0_CODE_START   = __itcm0_code_rom;
    __ROM_ITCM0_CODE_END     = __itcm0_code_rom_end;
    __RAM_DTCM0_DATA_START   = __dtcm0_data_start__;
    __ROM_DTCM0_DATA_START   = __dtcm0_data_rom;
    __ROM_DTCM0_DATA_END     = __dtcm0_data_rom_end;
    
    __BSS_SRAM_START         = __sram_bss_start;
    __BSS_SRAM_END           = __sram_bss_end;
    __BSS_SRAM_SIZE          = __sram_bss_end - __sram_bss_start;
    
    __BSS_SRAM_NC_START      = __non_cacheable_bss_start;
    __BSS_SRAM_NC_SIZE       = __non_cacheable_bss_end - __non_cacheable_bss_start;
    __BSS_SRAM_NC_END        = __non_cacheable_bss_end;

    __BSS_SRAM_SH_START      = __shareable_bss_start;
    __BSS_SRAM_SH_SIZE       = __shareable_bss_end - __shareable_bss_start;
    __BSS_SRAM_SH_END        = __shareable_bss_end;

    __RAM_INTERRUPT_START    = __interrupts_ram_start;
    __ROM_INTERRUPT_START    = __interrupts_rom_start;
    __ROM_INTERRUPT_END      = __interrupts_rom_end;

    __INIT_TABLE             = __init_table;
    __ZERO_TABLE             = __zero_table;
    
    __RAM_INIT               = 1;
    __ITCM_INIT              = 1;
    __DTCM_INIT              = 1;
    
    Fls_ACEraseRomStart         = __acfls_code_rom_start;
    Fls_ACEraseRomEnd           = __acfls_code_rom_end;
    Fls_ACEraseSize             = (__acfls_code_rom_end - __acfls_code_rom_start) / 4; /* Copy 4 bytes at a time*/

    Fls_ACWriteRomStart         = __acfls_code_rom_start;
    Fls_ACWriteRomEnd           = __acfls_code_rom_end;
    Fls_ACWriteSize             = (__acfls_code_rom_end - __acfls_code_rom_start) / 4; /* Copy 4 bytes at a time*/
    
    _ERASE_FUNC_ADDRESS_        = ADDR(.acfls_code_ram);
    _WRITE_FUNC_ADDRESS_        = ADDR(.acfls_code_ram);
    
    __ENTRY_VTABLE              = __ROM_INTERRUPT_START;
	
    __CORE0_VTOR             = __interrupts_rom_start;
    __CORE1_VTOR             = __interrupts_rom_start;

}

 1.2、startup_cm7.s文件需要调整一下，主要变化的内容：

 1.3、封装读/写/擦除的方法需要增加前缀，如

2、C40_IP组件添加和配置

 

 配置完成后要生成一下代码。

3、准备测试代码

/*==================================================================================================
*   Project              : RTD AUTOSAR 4.4
*   Platform             : CORTEXM
*   Peripheral           : S32K3XX
*   Dependencies         : none
*
*   Autosar Version      : 4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 2.0.1
*   Build Version        : S32K3_RTD_2_0_1_D2207_ASR_REL_4_4_REV_0000_20220707
*
*   (c) Copyright 2020 - 2021 NXP Semiconductors
*   All Rights Reserved.
*
*   NXP Confidential. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

/**
*   @file main.c
*
*   @addtogroup main_module main module documentation
*   @{
*/

/* Including necessary configuration files. */
#include "Mcal.h"
#include "Clock_Ip.h"
#include "C40_Ip.h"
#include "Power_Ip.h"
#include "Power_Ip_MC_ME.h"

volatile int exit_code = 0;
/* User includes */
#include "bsp_flash.h"
#include "SEGGER_RTT_Conf.h"
#include "SEGGER_RTT.h"
#include <string.h>

#define FLS_BUF_SIZE                 256U
#define FLS_SECTOR_ADDR              0x004FC000

uint8 TxBuffer[FLS_BUF_SIZE];
uint8 RxBuffer[FLS_BUF_SIZE];

void Fls_InitBuffers(void)
{
    uint32 Index;

    for (Index = 0U; Index < FLS_BUF_SIZE; Index++)
    {
        TxBuffer[Index] = (uint8)Index;
        RxBuffer[Index] = 0U;
    }
}

void bsp_flash_delay(uint32 delay)
{
    static volatile uint32 DelayTimer = 0;
    while(DelayTimer<delay)
    {
        DelayTimer++;
    }
    DelayTimer=0;
}

void LOG_INFO_Buffer(uint8_t *pData,uint16_t length)
{
	uint16_t i = 0;
	uint8_t value = 0;
	uint8_t LOG_Data[1024];
	memset(LOG_Data, 0, 1024);

	for(i=0;i<length;i++)
	{
		value =  (((*(pData+i))&0xF0) >> 4);
		LOG_Data[i*3 +0] = (value <= 9)? value +'0' : value -10 + 'A';
		value =  ((*(pData+i))&0x0F);
		LOG_Data[i*3 +1] = (value <= 9)? value +'0' : value -10 + 'A';
		LOG_Data[i*3 +2] = ' ';
	}
	SEGGER_RTT_printf(0, "%s\n", LOG_Data);
}

void flash_test(void)
{
	uint8_t res;
	/* Initialize buffers */
	Fls_InitBuffers();

	res = BspFlash_Erase(FLS_SECTOR_ADDR);
	if(res == true)
	{
		bsp_flash_delay(4800000);
	}

	res = BspFlash_Write(FLS_SECTOR_ADDR, &TxBuffer[0], FLS_BUF_SIZE);
	if(res == true)
	{
		bsp_flash_delay(4800000);
	}

}

/*!
  \brief The main function for the project.
  \details The startup initialization sequence is the following:
 * - startup asm routine
 * - main()
*/
int main(void)
{
    /* Write your code here */
	Clock_Ip_Init(&Clock_Ip_aClockConfig[0]);
	C40_Ip_Init(&C40ConfigSet_BOARD_InitPeripherals_InitCfg);

	flash_test();

    for(;;)
    {
        if(exit_code != 0)
        {
            break;
        }
    }
    return exit_code;
}

/** @} */

4、编译运行，及查看结果 

通过J-Flash读取芯片中的数据，可以看到数据写入成功了。