S32K3的中断向量表

S32K312的中断向量表所在文件名称是S32K312_COMMON.h

中断向量内容是：

/*!
 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
 * @{
 */

/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 229                /**< Number of interrupts in the Vector table */

typedef enum {
  /* Auxiliary constants */
  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */

  /* Core interrupts */
  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
  HardFault_IRQn               = -13,              /**< Cortex-M7 SV Hard Fault Interrupt */
  MemoryManagement_IRQn        = -12,              /**< Cortex-M7 Memory Management Interrupt */
  BusFault_IRQn                = -11,              /**< Cortex-M7 Bus Fault Interrupt */
  UsageFault_IRQn              = -10,              /**< Cortex-M7 Usage Fault Interrupt */
  SVCall_IRQn                  = -5,               /**< Cortex-M7 SV Call Interrupt */
  DebugMonitor_IRQn            = -4,               /**< Cortex-M7 Debug Monitor Interrupt */
  PendSV_IRQn                  = -2,               /**< Cortex-M7 Pend SV Interrupt */
  SysTick_IRQn                 = -1,               /**< Cortex-M7 System Tick Interrupt */

  /* Device specific interrupts */
  DMATCD0_IRQn                 = 4,                /**< DMA transfer complete and error CH0 */
  DMATCD1_IRQn                 = 5,                /**< DMA transfer complete and error CH1 */
  DMATCD2_IRQn                 = 6,                /**< DMA transfer complete and error CH2 */
  DMATCD3_IRQn                 = 7,                /**< DMA transfer complete and error CH3 */
  DMATCD4_IRQn                 = 8,                /**< DMA transfer complete and error CH4 */
  DMATCD5_IRQn                 = 9,                /**< DMA transfer complete and error CH5 */
  DMATCD6_IRQn                 = 10,               /**< DMA transfer complete and error CH6 */
  DMATCD7_IRQn                 = 11,               /**< DMA transfer complete and error CH7 */
  DMATCD8_IRQn                 = 12,               /**< DMA transfer complete and error CH8 */
  DMATCD9_IRQn                 = 13,               /**< DMA transfer complete and error CH9 */
  DMATCD10_IRQn                = 14,               /**< DMA transfer complete and error CH10 */
  DMATCD11_IRQn                = 15,               /**< DMA transfer complete and error CH11 */
  ERM_0_IRQn                   = 36,               /**< Single bit ECC error */
  ERM_1_IRQn                   = 37,               /**< Multi bit ECC error */
  MCM_IRQn                     = 38,               /**< Multi bit ECC error */
  STM0_IRQn                    = 39,               /**< Single interrupt vector for all four channels */
  SWT0_IRQn                    = 42,               /**< Platform watchdog initial time-out */
  CTI0_IRQn                    = 45,               /**< CTI Interrupt 0 */
  CTI1_IRQn                    = 46,               /**< CTI Interrupt 1 */
  FLASH_0_IRQn                 = 48,               /**< Program or erase operation is completed */
  FLASH_1_IRQn                 = 49,               /**< Main watchdog timeout interrupt */
  FLASH_2_IRQn                 = 50,               /**< Alternate watchdog timeout interrupt */
  RGM_IRQn                     = 51,               /**< Interrupt request to the system */
  PMC_IRQn                     = 52,               /**< One interrupt for all LVDs, One interrupt for all HVDs */
  SIUL_0_IRQn                  = 53,               /**< External Interrupt Vector 0 */
  SIUL_1_IRQn                  = 54,               /**< External Interrupt Vector 1 */
  SIUL_2_IRQn                  = 55,               /**< External Interrupt Vector 2 */
  SIUL_3_IRQn                  = 56,               /**< External Interrupt Vector 3 */
  EMIOS0_0_IRQn                = 61,               /**< Interrupt request 23,22,21,20 */
  EMIOS0_1_IRQn                = 62,               /**< Interrupt request 19,18,17,16 */
  EMIOS0_2_IRQn                = 63,               /**< Interrupt request 15,14,13,12 */
  EMIOS0_3_IRQn                = 64,               /**< Interrupt request 11,10,9,8 */
  EMIOS0_4_IRQn                = 65,               /**< Interrupt request 7,6,5,4 */
  EMIOS0_5_IRQn                = 66,               /**< Interrupt request 3,2,1,0 */
  EMIOS1_0_IRQn                = 69,               /**< Interrupt request 23,22,21,20 */
  EMIOS1_1_IRQn                = 70,               /**< Interrupt request 19,18,17,16 */
  EMIOS1_2_IRQn                = 71,               /**< Interrupt request 15,14,13,12 */
  EMIOS1_3_IRQn                = 72,               /**< Interrupt request 11,10,9,8 */
  EMIOS1_4_IRQn                = 73,               /**< Interrupt request 7,6,5,4 */
  EMIOS1_5_IRQn                = 74,               /**< Interrupt request 3,2,1,0 */
  WKPU_IRQn                    = 83,               /**< Interrupts from pad group 0,1,2,3, Interrupts from pad group 0_64, Interrupts from pad group 1_64, Interrupts from pad group 2_64, Interrupts from pad group 3_64 */
  CMU0_IRQn                    = 84,               /**< CMU0 interrupt */
  CMU1_IRQn                    = 85,               /**< CMU1 interrupt */
  CMU2_IRQn                    = 86,               /**< CMU2 interrupt */
  BCTU_IRQn                    = 87,               /**< An interrupt is requested when a conversion is issued to the ADC, An interrupt is requested when new data is available from ADC0 conversion, An interrupt is requested when new data is available from ADC1 conversion, An interrupt is requested when new data is available from ADC2 conversion, An interrupt is requested when the last command of a list is issued to the ADC,An Interrupt output for FIFO1,An Interrupt output for FIFO2 */
  LCU0_IRQn                    = 92,               /**< Interrupt 0, Interrupt 1 Interrupt 2 */
  LCU1_IRQn                    = 93,               /**< Interrupt 0, Interrupt 1 Interrupt 2 */
  PIT0_IRQn                    = 96,               /**< Interrupt for Channel0,Interrupt for Channel1,Interrupt for Channel2,Interrupt for Channel3,Interrupt for Channel4 */
  PIT1_IRQn                    = 97,               /**< Interrupt for Channel0,Interrupt for Channel1,Interrupt for Channel2,Interrupt for Channel3 */
  RTC_IRQn                     = 102,              /**< RTCF or ROVRF interrupt to be serviced by the system controller, APIF interrupt to be serviced by the system controller */
  FlexCAN0_0_IRQn              = 109,              /**< Interrupt indicating that the CAN bus went to Bus Off state */
  FlexCAN0_1_IRQn              = 110,              /**< Message Buffer Interrupt line 0-31,ORed Interrupt for Message Buffers */
  FlexCAN0_2_IRQn              = 111,              /**< Message Buffer Interrupt line 32-63 */
  FlexCAN1_0_IRQn              = 113,              /**< Interrupt indicating that the CAN bus went to Bus Off state */
  FlexCAN1_1_IRQn              = 114,              /**< Message Buffer Interrupt line 0-31 */
  FlexCAN1_2_IRQn              = 115,              /**< Message Buffer Interrupt line 32-63 */
  FlexCAN2_0_IRQn              = 116,              /**< Interrupt indicating that the CAN bus went to Bus Off state */
  FlexCAN2_1_IRQn              = 117,              /**< Message Buffer Interrupt line 0-31 */
  FlexCAN2_2_IRQn              = 118,              /**< Message Buffer Interrupt line 32-63 */
  FlexCAN3_0_IRQn              = 119,              /**< Interrupt indicating that the CAN bus went to Bus Off state */
  FlexCAN3_1_IRQn              = 120,              /**< Message Buffer Interrupt line 0-31 */
  FlexCAN4_0_IRQn              = 121,              /**< Interrupt indicating that the CAN bus went to Bus Off state */
  FlexCAN4_1_IRQn              = 122,              /**< Message Buffer Interrupt line 0-31 */
  FlexCAN5_0_IRQn              = 123,              /**< Interrupt indicating that the CAN bus went to Bus Off state */
  FlexCAN5_1_IRQn              = 124,              /**< Message Buffer Interrupt line 0-31 */
  FLEXIO_IRQn                  = 139,              /**< FlexIO Interrupt */
  LPUART0_IRQn                 = 141,              /**< TX and RX interrupt */
  LPUART1_IRQn                 = 142,              /**< TX and RX interrupt */
  LPUART2_IRQn                 = 143,              /**< TX and RX interrupt */
  LPUART3_IRQn                 = 144,              /**< TX and RX interrupt */
  LPUART4_IRQn                 = 145,              /**< TX and RX interrupt */
  LPUART5_IRQn                 = 146,              /**< TX and RX interrupt */
  LPUART6_IRQn                 = 147,              /**< TX and RX interrupt */
  LPUART7_IRQn                 = 148,              /**< TX and RX interrupt */
  I3C_IRQn                     = 160,              /**< I3C Interrupt */
  LPI2C0_IRQn                  = 161,              /**< LPI2C Master Interrupt */
  LPI2C1_IRQn                  = 162,              /**< LPI2C Master Interrupt */
  LPSPI0_IRQn                  = 165,              /**< LPSPI Interrupt */
  LPSPI1_IRQn                  = 166,              /**< LPSPI Interrupt */
  LPSPI2_IRQn                  = 167,              /**< LPSPI Interrupt */
  LPSPI3_IRQn                  = 168,              /**< LPSPI Interrupt */
  JDC_IRQn                     = 178,              /**< Indicates new data to be read from JIN_IPS register or can be written to JOUT_IPS register */
  ADC0_IRQn                    = 180,              /**< End of conversion, Error interrupt, Watchdog interrupt */
  ADC1_IRQn                    = 181,              /**< End of conversion, Error interrupt, Watchdog interrupt */
  LPCMP0_IRQn                  = 183,              /**< Async interrupt */
  LPCMP1_IRQn                  = 184,              /**< Async interrupt */
  FCCU_0_IRQn                  = 189,              /**< Interrupt request(ALARM state) */
  FCCU_1_IRQn                  = 190,              /**< Interrupt request(miscellaneous conditions) */
  HSE_MU0_TX_IRQn              = 192,              /**< ORed TX interrupt to MU-0 */
  HSE_MU0_RX_IRQn              = 193,              /**< ORed RX interrupt to MU-0 */
  HSE_MU0_ORED_IRQn            = 194,              /**< ORed general purpose interrupt request to MU-0 */
  HSE_MU1_TX_IRQn              = 195,              /**< ORed TX interrupt to MU-1 */
  HSE_MU1_RX_IRQn              = 196,              /**< ORed RX interrupt to MU-1 */
  HSE_MU1_ORED_IRQn            = 197,              /**< ORed general purpose interrupt request to MU-1 */
  SoC_IRQn                     = 212               /**< PLL LOL interrupt */
} IRQn_Type;