远程FPGA虚拟实验平台实现算术逻辑单元

算术逻辑单元

算术逻辑单元电路图

功能表

设计代码前需要具体分析各个功能实现时SR,SV,SL,M3,M2,M1,M0,S1,S0的取值，将其填入表格中。
具体取值如下表所示。

VirtualBoard模块代码

`default_nettype none 
module VirtualBoard (
    input  wire  CLOCK,        // 10 MHz Input Clock 
    input  wire [19:0] PB,     // 20 Push Buttons, logical 1 when pressed
    input  wire [35:0] S,      // 36 Switches
    output wire [35:0] L,      // 36 LEDs, drive logical 1 to light up
    output wire  [7:0] SD7,    // 8 common anode Seven-segment Display
    output wire  [7:0] SD6,
    output wire  [7:0] SD5,
    output wire  [7:0] SD4,
    output wire  [7:0] SD3,
    output wire  [7:0] SD2,
    output wire  [7:0] SD1,
    output wire  [7:0] SD0
); 

/** The input port is replaced with an internal signal **/

wire [3:0] ALUop= S[12:9];
wire [3:0] X = S[7:4];
wire [3:0] Y = S[3:0];
wire Cin=S[8];

/************* The logic of this experiment *************/
wire [3:0] A,B,F;
wire C0;
wire sign, zero, overflow, carryOut;
wire [4:0] resilt;
wire SR,SV,SL,M3,M2,M1,M0,S1,S0;
assign A[3] = (X[3]&SR)|(X[3]&SV)|(X[2]&SL);
assign A[2] = (X[3]&SR)|(X[2]&SV)|(X[1]&SL);
assign A[1] = (X[2]&SR)|(X[1]&SV)|(X[0]&SL);
assign A[0] = (X[1]&SR)|(X[0]&SV)|(0&SL);
assign B[3] = (Y[3]&M0)|(~Y[3]&M1);
assign B[2] = (Y[2]&M0)|(~Y[2]&M1);
assign B[1] = (Y[1]&M0)|(~Y[1]&M1);
assign B[0] = (Y[0]&M0)|(~Y[0]&M1);
assign C0 = (M3&Cin&M0)|M2|(M3&M1&(~Cin));
assign F=result[3:0];
assign carryOut =result[4];  
assign sign = F[3];
assign zero = (F==0) ? 1 : 0;  // ~|F;
assign overflow = (~A[3]) & ~B[3] & F[3] | (A[3]) & B[3] & ~F[3] ;

always @ALUop
begin 
  case(ALUop)
      4'b0000:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010000000;
		  end
	   4'b0001:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010000100;
		  end
		4'b0010:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010011000;
		  end
		4'b0011:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010000101;
		  end
		4'b0100:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010000110;
		  end		  
		4'b0101:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010000111;
		  end	
		4'b0110:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b100000000;
		  end	
		4'b0111:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b001000000;
		  end	
		4'b1000:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010001111;
		  end		
		4'b1001:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010010000;
		  end		
		4'b1010:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010001100;
		  end	
		4'b1011:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010100100;
		  end		
		4'b1100:begin
		  {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b010101000;
		  end		
      default: {SR,SV,SL,M3,M2,M1,M0,S1,S0}=9'b00000000;
     endcase
	end		
always_comb
begin
 case({S1,S0})
  2'b00:result=A+B+C0;
  2'b00:result=B&X;
  2'b00:result=X|B;
  2'b00:result=X^B;
  default:result={(5){1'bx}};
/****** Internal signal assign to output port *******/
assign L[3:0]  = B[3:0];
assign L[7:4]  = A[3:0]; 
assign L[12:9] = F[3:0];
assign L[26] = M3;
assign L[27] = M2;
assign L[28] = M1;
assign L[29] = M0;
assign L[24] = S1;
assign L[23] = S0;
assign L[32:30]={SR,SV,SL};
assign L[21:18] = {sign, zero, overflow, carryOut};

endmodule

验证，提交

在虚拟实验平台上下载电路，按ALUop的取值分别验证各个功能。最后按要求提交文件。