前言:这次没有实验材料所以是我自己乱写的,肚子饿了写得挺急的,有错记得dd我!
还有一个问题!welab平台里要拿测试的一百分,要改一段代码,就是上次的多功能运算代码里我提到的带借位减法的c0问题!注意看源代码的注释!
原理
ALU
就是在上次实验的基础上多了S1和S0,而且把所有开关装到一起去统称为ALUop了,就看起来很复杂其实蛮简单的。
源代码
ALU
VirtalBoard模块
这次sv也是要交的,所以复制粘贴的时候记得删改一下不要照搬哟!
`default_nettype none
module VirtualBoard (
input logic CLOCK, // 10 MHz Input Clock
input logic [19:0] PB, // 20 Push Buttons, logical 1 when pressed
input logic [35:0] S, // 36 Switches
output logic [35:0] L, // 36 LEDs, drive logical 1 to light up
output logic [7:0] SD7, // 8 common anode Seven-segment Display
output logic [7:0] SD6,
output logic [7:0] SD5,
output logic [7:0] SD4,
output logic [7:0] SD3,
output logic [7:0] SD2,
output logic [7:0] SD1,
output logic [7:0] SD0
);
localparam N =4;
wire [3:0] ALUop = S[12:9];//要求用ALUop来写啦
wire Cin = S[8];
wire [3:0] X = S[7:4];
wire [3:0] Y = S[3:0];
wire [N-1:0] A,B,F;
wire C0;
wire [N:0] result;
wire SR, SV, SL, M3, M2, M1, M0, S1, S0;
/*assign A = X;
assign B = Y & {N{M0}} | (~Y) & {N{M1}};
assign C0 = M2;//这个从实验材料里抄来的,没啥用的样子,大概是实验材料里没有加法器的版本是这样的*/
always @ ALUop
begin
case(ALUop)//根据那个表格自己写一下这些开关的1和0啥的
4'b0000: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010000000;
end
4'b0001: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010000100;
end
4'b0010: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010011000;
end
4'b0011: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010000101;
end
4'b0100: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010000110;
end
4'b0101: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010000111;
end
4'b0110: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b100000000;
end
4'b0111: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b001000000;
end
4'b1000: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010001111;
end
4'b1001: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010010000;
end
4'b1010: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010001100;
end
4'b1011: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010100100;
end
4'b1100: begin
{SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b010101000;
end
default: {SR, SV, SL, M3, M2, M1, M0, S1, S0}=9'b000000000;
endcase
end
assign A[3] = (X[3] & SR) | (X[3] & SV ) | (X[2] & SL);//就是上次的运算电路来着,没改
assign A[2] = (X[3] & SR) | (X[2] & SV ) | (X[1] & SL);
assign A[1] = (X[2] & SR) | (X[1] & SV ) | (X[0] & SL);
assign A[0] = (X[1] & SR) | (X[0] & SV ) | (0 & SL);
assign B[3] = (Y[3] & M0) | (~Y[3] & M1);
assign B[2] = (Y[2] & M0) | (~Y[2] & M1);
assign B[1] = (Y[1] & M0) | (~Y[1] & M1);
assign B[0] = (Y[0] & M0) | (~Y[0] & M1);
assign C0 = (Cin & M3) | M2;//这个是Cin=0时带借位减法有借位,而Cin=1时带借位减法无借位
/*assign C0 = ((~Cin) & M3 & M1)| (Cin & M3 & M0) | M2;//这个是Cin=1时带借位减法有借位,而Cin=0时带借位减法无借位*/
always_comb
begin
case({S1,S0})
2'b00: result = A + B + C0;
2'b01: result = X & B;
2'b10: result = X | B;
2'b11: result = X ^ B;
default: result = {(N+1){1'bx}};
endcase
end
assign F = result[N-1:0];
wire sign, zero, overflow, carryOut;
assign sign = F[N-1];
assign zero = (F==0) ? 1 : 0; // ~|F;
assign overflow = (~A[N-1]) & ~B[N-1] & F[N-1] | (A[N-1]) & B[N-1] & ~F[N-1] ;//就是改成了N啥的,没大变化
assign carryOut = result[N];
assign L[3:0] = B[3:0];
assign L[7:4] = A[3:0];
assign L[12:9] = F;
assign L[21:18] = {sign, zero, overflow, carryOut};
assign L[24:23] = {S1, S0};
assign L[29:26] = {M0, M1, M2, M3};
assign L[32:30] = {SR, SV, SL};
endmodule
测试/保存/提交
这次提交回放记录有点问题,显示连不上考核中心,可以在用户中心里提交试试看,好像可以。
welab实验平台里如果是92.31分,就是c0的问题,注意看代码,用“assign C0 = (Cin & M3) | M2”这段。落泪了,多功能运算器里要拿100分不能这么写,到这儿又要反着来,这玩意儿debug花了我二十分钟才找出来,但是下周的数据通路好像又不用,要用的话在下次里的说。