前一段时间因为比较烦躁,对这个的理解不够,导致盲目瞎做,出了很多问题,就一直没有接着往下做,今天仔细想来一下发现其实很简单
代码如下
time /
module sysclk(CLK , // clock
OV ); // overflow
input CLK;
output OV;
parameter MAX_VAL = 25_000_000;
reg [32-1:0] CNTVAL;
reg OV;
always @ (posedge CLK) begin
if(CNTVAL >= MAX_VAL)
CNTVAL = 0;
else
CNTVAL = CNTVAL + 1'b1;
end
always @ (CNTVAL) begin
if(CNTVAL == MAX_VAL)
OV = 1'b1;
else
OV = 1'b0;
end
endmodule
module shift_register(
IN ,//input
OUT ,//output
EN ,
DIR ,
CLK );
input IN,CLK ,EN,DIR;
output [long-1:0] OUT ;
parameter long = 8;
reg [long-1:0] shift;
//reg [long-1:0] OUT;
assign OUT[long-1:0] = shift[long-1:0];
always @(posedge CLK) begin
if(EN) begin
if(DIR) begin
shift[long-1:1] = shift[long-2:0];
shift[0]=IN;
end
else begin
shift[long-2:0] = shift[long-1:1];
shift[7]=IN;
end
end
else
shift[long-1:0] = shift[long-1:0];
end
endmodule