HDL-Bits --finite state machine

simple FSM1(asynchronous reset)

问题描述

        这是一个有两种状态,一个输入,一个输出的MOORE状态机。reset时,状态变为B。和FSM1相同,但是使用了异步时钟。

代码

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;
	
    //第一段时序逻辑电路
    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset) begin// State flip-flops with asynchronous reset
         	state <= B;
        end
        else begin
            state <= next_state;
        end
    end    
    
    //组合逻辑电路:状态的转移
    always @(*) begin    // This is a combinational always block
        
            case(state)// State transition logic
        		A : 
                    if(in) begin
                        next_state = A;
                    end
                	else begin
                        next_state = B;
                    end
            	B : 
                    if(in) begin
                        next_state = B;
                    end
                	else begin
                        next_state = A;
                    end
                default:;
        	endcase
         
    end

	//第三段;状态输出
 	always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset) begin// State flip-flops with asynchronous reset
         	out <= 1'b1;
        end
        else begin
            case(next_state)
                A : out <= 1'b0;
                B : out <= 1'b1;
                default: out <= 1'b1;
            endcase
        end
    end    
endmodule

fsm1(synchronous reset)

问题描述

        这是一个有两种状态,一个输入,一个输出的MOORE状态机。reset时,状态变为B。和FSM1相同,但是使用了同步时钟。

代码

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    parameter A = 1'B0;
    parameter B = 1'B1;
    // Fill in state name declarations

    reg present_state, next_state;
	always @(posedge clk) begin
    	if (reset) begin
            present_state <= B;
        end else begin
            present_state <= next_state; 
        end
    end
    always @(*) begin
            case (present_state) // Fill in state transition logic
                A : 
                    if(in) begin
                        next_state = A;
                    end
                	else begin
                        next_state = B;
                    end
                B : 
                    if(in) begin
                        next_state = B;
                    end
                	else begin
                        next_state = A;
                    end
                default:;
            endcase
           // present_state = next_state;  // State flip-flops 
    end
    //three
	always @(posedge clk) begin
        if(reset) begin
            out <= 1'b1;
        end
        else begin
        case(next_state)
            	 A : out <= 1'b0;
            	 B : out <= 1'b1;
            default: out <= out;
        endcase
        end
    end
endmodule

FSM2(asynchronous reset)

问题描述

代码

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(posedge clk, posedge areset) begin
        if(areset) begin// State transition logic
            state <= OFF;
        end
        else begin 
            state <= next_state;
        end
    end

    always @(*) begin
        // State transition logic
            case(state)
                ON :
                    if(k) begin
                        next_state = OFF;
                    end
               	 	else begin
                    	next_state = ON;
                	end
                OFF :
                    if(!j) begin
                        next_state = OFF;
                    end
               	 	else begin
                    	next_state = ON;
                	end
               default:;
            endcase
    end
    
    always @(posedge clk, posedge areset) begin
        if(areset) begin// State transition logic
            out <= 1'b0;
        end
        else begin
            case(next_state)
                ON  :  out <= 1'b1;
                OFF :  out <= 1'b0;
                default : ;
            endcase
        end// State flip-flops with asynchronous reset
    end


endmodule

出现问题

  error(10028): cant resolve multiple constant driveers for net

        解决:在不同的always逻辑块中,对同一个reg变量进行赋值,在多个always逻辑块中同时并行工作,出现冲突。对一个变量只需在一个always块中进行赋值。

FSM2(synchronous reset)

问题描述

代码

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(posedge clk) begin
        if(reset) begin// State transition logic
            state <= OFF;
        end
        else begin 
            state <= next_state;
        end
    end

    always @(*) begin
        // State transition logic
            case(state)
                ON :
                    if(k) begin
                        next_state = OFF;
                    end
               	 	else begin
                    	next_state = ON;
                	end
                OFF :
                    if(!j) begin
                        next_state = OFF;
                    end
               	 	else begin
                    	next_state = ON;
                	end
               default:;
            endcase
    end

    always @(posedge clk) begin
        if(reset) begin
            out <= 1'b0;
        end
        else begin
            case(next_state)
                ON  :  out <= 1'b1;
                OFF :  out <= 1'b0;
                default : ;
            endcase
        end// State flip-flops with synchronous reset
    end

    // Output logic
    // assign out = (state == ...);

endmodule

FSM3comb

问题描述

 代码

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;
 // State transition logic: next_state = f(state, in)
    always @(*)
        begin
            case(state)
                A : 
                    if(in) begin
                        next_state = B;
                    end
                	else begin
 						next_state = A;                       
                    end
                B : 
                    if(in) begin
                        next_state = B;
                    end
                	else begin
 						next_state = C;                       
                    end
                C : 
                    if(in) begin
                        next_state = D;
                    end
                	else begin
 						next_state = A;                       
                    end
               	D : 
                    if(in) begin
                        next_state = B;
                    end
                	else begin
 						next_state = C;                       
                    end
                  default:;
            endcase
        end
   

    // Output logic:  out = f(state) for a Moore state machine
	always @(*)
        begin
            case(state)
                A : out = 0;
                B : out = 0;
                C : out = 0;
               	D : out = 1;
               default:;
            endcase
        end
endmodule

FSM3onehot

问题描述

derive equations by inspection 

        独热码编码保证了只有一个状态位为1,这意味着决定状态机是否在特定状态是检测一个状态位,而不是所有状态位。通过检查状态转移图中每个状态的传入方向获得状态转移的逻辑关系。

        例如,在上水的状态机中,如何让状态机到达状态A呢?这必须使用两个传入状态中的一条:“当前状态A与上in = 0”或者“当前状态C与上in = 0“。由于独热码编码中,测试“当前处于状态A”的逻辑方程只是状态A的状态位。这导致状态位A的下一个状态的最终逻辑方程:next_state[0] = state[0]&(~in) | state[2]&(~in)。one-hot编码保证一次最多有一个子句(产品项)是“活动的”,因此这些子句只能被组合在一起。

        当习题要求”通过检查“获得状态转移方程时,是使用了特殊的方法。判断器会测试非独热输入来确保你的逻辑关系遵循这个方法,而不是对其他位的非法(非独热码)组合做一些其他操作(重置状态机)。

        尽管对RTL级设计(逻辑分析)来说这个算法并不是必须的,但是这说明了为什么独热码有更加简单的逻辑(在牺牲更多存储的代价上),这也经常出现在逻辑考试题中。

代码

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] =  (~in & state[A]) | (state[C] & ~in);
    assign next_state[B] =  (in & state[A]) | (in & state[B]) | (in & state[D]);
    assign next_state[C] =   (~in & state[B]) | (~in & state[D]);
    assign next_state[D] =  in & state[C];

    // Output logic: 
    assign out = state[D];

endmodule

最后的输出多观察位与状态之间的关系,可以很简洁的。

FSM3

问题描述

代码

module top_module(
    input clk,
    input in,
    input areset,
    output out); //

    parameter A = 4'b0001, B = 4'b0010, C = 4'b0100, D = 4'b1000;
    reg [3:0] state, next_state;
    // State transition logic
    always @(posedge clk , posedge areset)
        begin
            if(areset) begin
               state <= A; 
            end
            else begin
                state <= next_state;
            end
        end
    // State flip-flops with asynchronous reset
    always @(*)
        begin
            case(state)
                A :
                    if(in) begin
                        next_state <= B;
                    end
                	else begin
                    	next_state <= A;
                	end
                B :
                    if(in) begin
                        next_state <= B;
                    end
                	else begin
                    	next_state <= C;
                	end
                C :
                    if(in) begin
                        next_state <= D;
                    end
                	else begin
                    	next_state <= A;
                	end
                D :
                    if(in) begin
                        next_state <= B;
                    end
                	else begin
                    	next_state <= C;
                	end
                default:;
            endcase
        end
    // Output logic
	always @(posedge clk , posedge areset)
        begin
            case(state)
                A : out <= 1'b0;
                B : out <= 1'b0;
                C : out <= 1'b0;
                D : out <= 1'b1;
                default : out <= 1'b0;
            endcase
            
        end
endmodule

遇到问题

错误代码:Error (10200): Verilog HDL Conditional Statement error at count.v(90)(即倒数第三行if(add)处): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

表示边沿触发与if-else中的语句的触发条件冲突。本题在编写的时候出现,always语句触发条件中使用的是negedge areset(下降沿触发),但是在if中是areset,高电平触发。

FSM3S

问题描述

代码

module top_module(
    input clk,
    input in,
    input reset,
    output out); //

    parameter A = 4'b0001, B = 4'b0010, C = 4'b0100, D = 4'b1000;
    reg [3:0] state, next_state;
    // State transition logic
    always @(posedge clk )
        begin
            if(reset) begin
               state <= A; 
            end
            else begin
                state <= next_state;
            end
        end
    // State flip-flops with asynchronous reset
    always @(*)
        begin
            case(state)
                A :
                    if(in) begin
                        next_state <= B;
                    end
                	else begin
                    	next_state <= A;
                	end
                B :
                    if(in) begin
                        next_state <= B;
                    end
                	else begin
                    	next_state <= C;
                	end
                C :
                    if(in) begin
                        next_state <= D;
                    end
                	else begin
                    	next_state <= A;
                	end
                D :
                    if(in) begin
                        next_state <= B;
                    end
                	else begin
                    	next_state <= C;
                	end
                default:;
            endcase
        end
    // Output logic
	always @(posedge clk )
        begin
            case(next_state)
                A : out <= 1'b0;
                B : out <= 1'b0;
                C : out <= 1'b0;
                D : out <= 1'b1;
                default : out <= 1'b0;
            endcase
            
        end
endmodule

问题提出:

最后一个判断中什么时候用state判断,什么时候选用next_state

Lemmings

问题描述

代码

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right); //  

    parameter LEFT=0, RIGHT=1;
    reg state, next_state;
 	
    always @(posedge clk, posedge areset) begin
        if(areset) begin// State flip-flops with asynchronous reset
        	state <= LEFT;
        end
        else begin
            state <= next_state;
    end
    end
    always @(*) begin
        case({bump_left, bump_right})// State transition logic
            2'b00 : next_state <= state;
            2'b01 : next_state <= LEFT;
            2'b10 : next_state <= RIGHT;
            2'b11 : next_state <= ~state;
            default :;
        endcase
    end

    // Output logic
     assign walk_left = (state == LEFT);
     assign walk_right = (state == RIGHT);

endmodule

lemmings2

问题描述

代码

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 

    parameter LEFT = 3'b001, RIGHT = 3'b010, LEFT_FALLING = 3'b011, RIGHT_FALLING = 3'b100;
    reg [2:0] state, next_state;
   
    always @(posedge clk, posedge areset) begin
        if(areset) begin
            state <= LEFT;
        end
        else begin
            state <= next_state;
        end
    end
    always @(*) begin
        case(state)
            LEFT :
                if(ground) begin
                    next_state = bump_left ? RIGHT : LEFT;
                end
                else begin
                    next_state = LEFT_FALLING;
                end
            RIGHT : 
                if(ground) begin
                    next_state = bump_right ? LEFT : RIGHT;
                end
                else begin
                    next_state = RIGHT_FALLING;
                end
            LEFT_FALLING : 
                if(ground) begin
                    next_state = LEFT;
                end
                else begin
                    next_state = LEFT_FALLING;
                end
            RIGHT_FALLING :
                if(ground) begin
                    next_state =  RIGHT ;
                end
                else begin
                    next_state = RIGHT_FALLING;
                end
        endcase
    end
    
    assign    walk_left   = (state == LEFT);
    assign    walk_right  = (state == RIGHT);
    assign    aaah 		  = (state == LEFT_FALLING) || (state == RIGHT_FALLING);

    
endmodule

Lemmings3

问题描述

代码

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 

    parameter LEFT = 3'd1, RIGHT = 3'd2, LEFT_FALLING = 3'd3, RIGHT_FALLING = 3'd4,LEFT_DIG = 3'd5, RIGHT_DIG = 3'd6;
    reg [2:0] state, next_state;
    //状态转移时序电路
    always @(posedge clk, posedge areset)
        begin
            if(areset) begin
                state <= LEFT;
            end
            else begin
                state <= next_state;
            end
        end
    
    always @(*)
        begin
            case(state)
                LEFT :
                    if(ground) begin
                        next_state = dig ? LEFT_DIG : (bump_left ? RIGHT : LEFT);
                    end
               		else begin
                   		next_state = LEFT_FALLING;
               		end
                RIGHT :
                    if(ground) begin
                        next_state = dig ? RIGHT_DIG : (bump_right ? LEFT : RIGHT);
                    end
               		else begin
                   		next_state = RIGHT_FALLING;
               		end
                LEFT_FALLING :
                    if(ground) begin
                        next_state = LEFT;
                    end
                	else begin
                        next_state = LEFT_FALLING;
                    end
                RIGHT_FALLING :
                    if(ground) begin
                        next_state = RIGHT;
                    end
                	else begin
                        next_state = RIGHT_FALLING;
                    end
                LEFT_DIG :
                    if(ground) begin
                        next_state = LEFT_DIG;
                    end
                	else begin
                        next_state = LEFT_FALLING;
                    end
                RIGHT_DIG :
                    if(ground) begin
                        next_state = RIGHT_DIG;
                    end
                	else begin
                        next_state = RIGHT_FALLING;
                    end
            endcase
        end
    assign walk_left   = (state == LEFT);
    assign walk_right  = (state == RIGHT);
    assign aaah		   = (state == LEFT_FALLING) || (state == RIGHT_FALLING);
    assign digging	   = (state == LEFT_DIG) ||  (state == RIGHT_DIG); 
endmodule

Lemmings4

问题描述

代码

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
	
    parameter LEFT = 3'd1, RIGHT = 3'd2, LEFT_FALLING = 3'd3, RIGHT_FALLING = 3'd4,LEFT_DIG = 3'd5, RIGHT_DIG = 3'd6, DEAD = 3'D7;
    reg count_flag;
    reg [9:0] clk_count;
    reg [2:0] state, next_state;
    //状态转移时序电路
    always @(posedge clk, posedge areset)
        begin
            if(areset) begin
                state <= LEFT;
            end
            else begin
                state <= next_state;
            end
        end
    
      always @(posedge clk, posedge areset)
        begin
            if(areset) 
                clk_count <= 10'b0;
            else if((next_state == LEFT_FALLING) || (next_state == RIGHT_FALLING)) 
                	clk_count <= clk_count + 1'b1;
            	else 
                	clk_count <= 10'b0;
        end
    
    //组合逻辑电路执行状态转移
    always @(*)
        begin
            next_state = LEFT;
            case(state)
                LEFT :
                    if(ground) begin
                        next_state = dig ? LEFT_DIG : (bump_left ? RIGHT : LEFT);
                    end
               		else begin
                   		next_state = LEFT_FALLING;
               		end
                RIGHT :
                    if(ground) begin
                        next_state = dig ? RIGHT_DIG : (bump_right ? LEFT : RIGHT);
                    end
               		else begin
                   		next_state = RIGHT_FALLING;
               		end
                LEFT_FALLING :
                    if(ground) begin
                        if(clk_count <= 10'd20)
                        	next_state = LEFT;
                        else 
                            next_state = DEAD;
                    end
                	else begin
                        next_state = LEFT_FALLING;
                    end
                RIGHT_FALLING :
                    if(ground) begin
                        if(clk_count <= 10'd20) 
                        	next_state = RIGHT;
                        else 
                            next_state = DEAD;
                    end
                	else begin
                        next_state = RIGHT_FALLING;
                    end
                LEFT_DIG :
                    if(ground) begin
                        next_state = LEFT_DIG;
                    end
                	else begin
                        next_state = LEFT_FALLING;
                    end
                RIGHT_DIG :
                    if(ground) begin
                        next_state = RIGHT_DIG;
                    end
                	else begin
                        next_state = RIGHT_FALLING;
                    end
                DEAD :
                    next_state = DEAD;
                default :
                    next_state = LEFT;
            endcase
        end
    //(state == DEAD) ? 1'b0 :
    assign walk_left   =  (state == LEFT);
    assign walk_right  =  (state == RIGHT);
    assign aaah		   =  ((state == LEFT_FALLING || state == RIGHT_FALLING));
    assign digging	   =  ((state == LEFT_DIG || state == RIGHT_DIG)); 

错误解决:

        开始的时候经常出现以下仿真时序问题,多次检验状态跳转逻辑正确。

 最后发现在状态转移时的判断出现问题:
        在该程序中,我们使用的是moore状态机,其输出只与当前状态有关,只有在状态跳转到下一个周期后,输出才会变化(使用的是时序逻辑)。简单理解:如果一个时钟周期中输出发生变化,则输出与输入有关,则是mealy状态机)。将判断中的state变成next_state仿真成功。

always @(posedge clk, posedge areset)
        begin
            if(areset) 
                clk_count <= 10'b0;
            else if((next_state == LEFT_FALLING) || (next_state == RIGHT_FALLING)) 
                	clk_count <= clk_count + 1'b1;
            	else 
                	clk_count <= 10'b0;
        end

*mealy状态机比Moore状态机的状态个数少

*mealy状态机比moore状态机的输出要早一个时钟周期

Fsm onehot

问题描述

代码

module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
	
    //parameter   S0 = 10'b0000000001, S1 = 10'b0000000010, S2 = 10'b0000000100,
    //		    S3 = 10'b0000001000, S4 = 10'b0000010000, S5 = 10'b0000100000,
    //			S6 = 10'b0001000000, S7 = 10'b0010000000, S8 = 10'b0100000000, S9 = 10'b1000000000,
    
    assign next_state[0] = (~in & state[0]) | (~in & state[1]) | (~in & state[2]) | (~in & state[3]) | (~in & state[4]) | (~in & state[7]) | (~in & state[8]) | (~in & state[9]);
    assign next_state[1] = (in & state[0])  | (in & state[8]) | (in & state[9]);
    assign next_state[2] = (in & state[1]);
    assign next_state[3] = (in & state[2]);
    assign next_state[4] = (in & state[3]);
    assign next_state[5] = (in & state[4]);
    assign next_state[6] = (in & state[5]);
    assign next_state[7] = (in & state[6]) | (in & state[7]);
    assign next_state[8] = (~in & state[5]);
    assign next_state[9] = (~in & state[6]);
    
    assign out1 = (state[8] | state[9]);
    assign out2 = (state[7] | state[9]);
endmodule

Fsm ps2

问题描述

 

Fsm ps2data

代码

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    reg [7:0] state, next_state;
    parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3;
    // State transition logic (combinational)
    always @(*)
        begin
            case(state)
                s0 :
                    next_state = in[3] ? s1 : s0;
                s1 :
                    next_state = s2;
                s2 :
                    next_state = s3;
                s3 :
                    next_state = in[3] ? s1 : s0;
                
            endcase
        end
    // State flip-flops (sequential)
 	always @(posedge clk)
        begin
            if(reset) begin
                state <= s0;
            end
            else begin
                state <= next_state;
            end
        end
    // Output logic
                assign done = (state == s3);
endmodule

问题描述

代码

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
	
    reg [3:0] state, next_state;
    //reg [7:0] in1, in2, in3;
    parameter s0 = 4'b0001, s1 = 4'b0010, s2 = 4'b0100, s3 = 4'b1000;
    // FSM from fsm_ps2
    always @(posedge clk)
        begin
            if(reset) begin
                state <= s0;
            end
            else begin
                state <= next_state;
            end
        end
    always @(*)
        begin
            case(state)
                s0: if(in[3]) begin
                        next_state = s1;
                    end
                	else begin
                    	next_state = s0;
                    end
                s1: next_state = s2;
                s2: next_state = s3;
                s3: if(in[3]) begin
                        next_state = s1;
                    end
                	else begin
                    	next_state = s0;
                    end
                default : next_state = s0;
            endcase
        end
    // New: Datapath to store incoming bytes.
    always @(posedge clk)
        begin
            if(reset) begin
                done      <= 0; 
            end
            else begin
            case(next_state)
                s0,s1,s2 :begin
                    done      <= 0;
                    out_bytes <= {out_bytes[15:0], in[7:0]};
                    end
                s3 : begin
                    done      <= 1;
                    out_bytes <= {out_bytes[15:0], in[7:0]};
                     end
                default: done <= 0;                  
            endcase
            end
        end
endmodule

Fsm serial

问题描述

代码

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter s0 = 1, s1 = 2, s2 = 3, s3 = 4, s4 = 5, s5 = 6, s6 = 7, s7 = 8, s8 = 9, s9 = 10, s10 = 11, s11 = 12;
    reg [4:0] state,next_state;
    always @(posedge clk)
        begin
            if(reset) begin
                state <= s0;
            end
            else begin
               state <= next_state; 
            end
        end
    
    always @(*)
        begin
            case(state)
                s0 : next_state =  in ? s0 : s1;
                s1 : next_state = s2;
                s2 : next_state = s3;
                s3 : next_state = s4;
                s4 : next_state = s5;
                s5 : next_state = s6;
                s6 : next_state = s7;
                s7 : next_state = s8;
                s8 : next_state = s9;
                s9 : next_state =  in ? s10 : s11;//stop位,1 done =1(s10), 0 error(s11) 并一直寻找  1
                s10: next_state =  in ? s0 : s1;  //done =1(s10)
                s11: next_state =  in ? s0 : s11 ;
                default:next_state = s0;
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset) begin
                done <= 0;
            end
            else begin
                case(next_state)
                     //s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s11 : done <= 0;
                     s10 : done <=  1 ;
                     default:done <= 0;
                     endcase
            end
        end
endmodule

Fsm serialdata

问题描述

代码

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
	parameter  s0  = 12'b000000000001, 
    			s1  = 12'b000000000010,
    			s2  = 12'b000000000100, 
    			s3  = 12'b000000001000,
    			s4  = 12'b000000010000, 
    			s5  = 12'b000000100000,
    			s6  = 12'b000001000000,
    			s7  = 12'b000010000000,
    			s8  = 12'b000100000000,
    			s9  = 12'b001000000000,
    			s10 = 12'b010000000000,
    			s11 = 12'b100000000000;
    
    wire [7:0] 	out_byte_temp;		
    reg [11:0] state,next_state;
    // Use FSM from Fsm_serial
    always @(posedge clk)
        begin
            if(reset) 
                 state <= s0;
            else 
                 state <= next_state;
        end
    // New: Datapath to latch input bits.
    always @(*)
        begin
            case(state) 
                s0 : next_state = in ? s0 : s1;
                s1 : next_state = s2;
                s2 : next_state = s3;
                s3 : next_state = s4;
                s4 : next_state = s5;
                s5 : next_state = s6;
                s6 : next_state = s7;
                s7 : next_state = s8;
                s8 : next_state = s9; 
                s9 : next_state = in ? s10 : s11;
                s10 : next_state = in ? s0 : s1; //stop =1
                s11 : next_state = in ? s0 : s11;//stop =0
                default:next_state = s0 ;
            endcase
        end
    
    always @(posedge clk)
        begin
            if(reset)
                 done <= 1'b0;
            else begin
                case(next_state)
					s10 : begin
                        done <= 1'b1;
                        out_byte <= out_byte_temp;
                    end
                    default : begin
                        done <= 1'b0;
                        out_byte <= 8'b0;
                    end
                endcase
            end
        end
    always @(posedge clk)
        begin
            if(reset) begin
                out_byte_temp <= 0;
            end
            else begin
                if(state == s10) 
                    out_byte_temp <= {in, out_byte_temp[7:1]};
                else 
                    out_byte_temp <= out_byte_temp;
            end
        end
  //  assign  done = (state == s10);
endmodule

FSM serialdp

问题描述

代码

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
	wire odd, oddreset;
    reg [3:0] state, next_state;
    reg [3:0] cnt;
    reg [7:0] out_byte_temp;
    parameter START = 4'b0001, DATA = 4'b0010, STOP = 4'b0100, ERROR = 4'b1000;
    assign oddreset = reset | (!(state == DATA));
    // Modify FSM and datapath from Fsm_serialdata
    always @(posedge clk) 
        begin
        if(reset) begin
           state <= START; 
        end
        else begin
            state <= next_state;
        end
    	end
    
    always @(*) 
        begin
            case(state) 
                START :  next_state = in ? START : DATA;
                DATA  :  begin
                    if(cnt == 4'd9) begin
                        if(in) 
                        	next_state = STOP;
                    	else 
                        	next_state = ERROR;
                    end
                    else begin
                        next_state = DATA;
                    end
                end
                STOP  :  next_state = in ? START : DATA;
                ERROR :  next_state = in ? START : ERROR;
                default : next_state = START;
            endcase
    	end
    
    always @(posedge clk) 
        begin
        if(reset) begin
           done <= 1'b0;
           //out_byte <= 8'b0;
        end
        else begin
            case(next_state)
                STOP  : begin
                    if(odd) 
                        done <= 1'b1;
                	else 
                        done <= 1'b0;
                    out_byte <= out_byte_temp;
                end
                default : begin
                    done <= 1'b0;
                    out_byte <= 8'b0;
                end
            endcase
        end
    	end
     always @(posedge clk) 
        begin
        if(reset) begin
           cnt <= 4'b0; 
        end
        else begin
            if((state == DATA) ) begin
            	cnt <= cnt + 1'b1;
            end
            else begin
                cnt <= 4'b0;
            end
        end
    	end
    
     always @(posedge clk) 
        begin
        if(reset) begin
           out_byte_temp <= 8'b0;
        end
        else begin
            if((next_state == DATA) && (cnt <= 4'd7)) begin
                out_byte_temp <= {in, out_byte_temp[7:1]};
            end
            else begin
                out_byte_temp <= out_byte_temp;
            end
        end
    	end
    // New: Add parity checking.
    parity i1(clk, oddreset, in, odd);
endmodule

Fsm serialdata

问题描述

代码 

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    parameter START = 4'b0001, DATA = 4'b0010, STOP = 4'b0100, ERROR = 4'b1000;
    reg [3:0] cnt;
    reg [7:0] out_byte_temp;
    reg [3:0] state, next_state;
    // Use FSM from Fsm_serial
    
    always @(posedge clk) begin
        if(reset) begin
            state <= START;
        end
        else begin
            state <= next_state;
        end
    end
    
    always @(*) begin
        case(state) 
            START : next_state = in ? START : DATA;
            DATA  :
                if(cnt == 8) begin
                    next_state = in ? STOP : ERROR;
                end
            	else begin
                    next_state =  DATA;
                end
            STOP  : next_state = in ? START : DATA;
            ERROR : next_state = in ? START : ERROR;
            default : next_state = START;
        endcase
    end
    always @(posedge clk) begin
        if(reset) begin
            cnt <= 'b0;
            out_byte_temp <= 'b0;
        end
        else begin
            if(state == DATA && cnt <= 8'd7) begin
                cnt <= cnt + 1'b1;
                out_byte_temp <= {in, out_byte_temp[7:1]};
            end
            else begin
                cnt <= 'b0;
                out_byte_temp <= out_byte_temp;
            end
        end
    end
    // New: Datapath to latch input bits.             
    always @(posedge clk) begin
        if(reset) begin
            done <= 0;
            out_byte <= 8'b0;
        end
        else begin
            case(next_state) 
                STOP : begin
                    done <= 1;
                    out_byte <= out_byte_temp;
                end
                default : begin
            		done <= 0;
            		out_byte <= 8'b0;
        		end
            endcase
        end
    end
endmodule

Fsm hdlc

问题描述

代码

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);

    parameter 	START  = 10'b0000000001, DATA_1 = 10'b0000000010, 
    			DATA_2 = 10'b0000000100, DATA_3 = 10'b0000001000, 
    			DATA_4 = 10'b0000010000, DATA_5 = 10'b0000100000, 
    			DATA_6 = 10'b0001000000, DISC   = 10'b0010000000, 
    			FLAG   = 10'b0100000000, ERROR  = 10'b1000000000;
   // reg [3:0] cnt;
    reg [9:0]state, next_state;
    
    always @(posedge clk) begin
        if(reset) begin
            state <= START;
        end
        else begin
            state <= next_state;
        end
    end
    
    always @(*) begin
        case(state) 
            START  : next_state = in ? DATA_1 : START;
            DATA_1 : next_state = in ? DATA_2 : START;
            DATA_2 : next_state = in ? DATA_3 : START;
            DATA_3 : next_state = in ? DATA_4 : START;
            DATA_4 : next_state = in ? DATA_5 : START;
            DATA_5 : next_state = in ? DATA_6 : DISC; // in= 0 : disc; in= 1 : 往下判断是否为fl
            DISC   : next_state = in ? DATA_1 : START;
            DATA_6 : next_state = in ? ERROR : FLAG;
            FLAG   : next_state = in ? DATA_1 : START;
            ERROR  : next_state = in ? ERROR  : START;  
            default : next_state = START;
        endcase
    end
       
    always @(posedge clk) begin
        if(reset) begin
            disc <= 'b0;
            flag <= 'b0;
            err <= 'b0;
        end
        else begin
            case(next_state)
                DISC : begin
                    disc <= 'b1;
            		flag <= 'b0;
            		err  <= 'b0;
                end
                FLAG : begin
                    disc <= 'b0;
            		flag <= 'b1;
            		err  <= 'b0;
                end
                ERROR : begin
                    disc <= 'b0;
            		flag <= 'b0;
            		err  <= 'b1;
                end
                default :begin
                    disc <= 'b0;
            		flag <= 'b0;
            		err  <= 'b0;
                end
                    
            endcase
        end
    end
endmodule

Exams/ece241 2013 q8

问题描述 

代码

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
	
    parameter START = 4'b0001, DATA1 = 4'b0010, DATA2 = 4'b0100, STOP = 4'b1000;
    reg [3:0] state, next_state;
    always @(posedge clk , negedge aresetn)
        begin
            if(!aresetn) begin
                state <= START;
            end
            else begin
                state <= next_state;
            end
        end
    
    always @(*)
        begin
            case(state)
                START : next_state = x ? DATA1 : START; //1?
                DATA1 : next_state = x ? DATA1 : DATA2; //0?
                DATA2 : next_state = x ? DATA1 : START; //1?
               // STOP  : next_state = x ? DATA1  : DATA2;
                default : next_state = START;
            endcase
        end
    
    //assign z = ((state == DATA2) && x ==1) ? 1 : 0;
    always @(*)
        begin
            if(!aresetn) begin
                z <= 'b0;
            end
            else begin
                case(state)
                  DATA2   : z = x ? 'b1 :'b0;
                  default: z = 'b0;
                endcase
            end
        end
endmodule

问题解决

当检测到101时,立刻输出逻辑1,因此最后一个状态判断的时候通过always@(*)实现,不通过时钟信号的变换

serial two‘s complementer(mealy fsm)

问题描述

代码

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    reg  [1:0] state, next_state;
    parameter A = 2'b01, B = 2'b10;
 	always @(posedge clk, posedge areset) 
        begin
            if(areset) begin
                state <= A;
            end
            else begin
                state <= next_state;
            end
        end
    always @(*) begin
        case(state) 
            A : next_state = x ? B: A;
            B : next_state = B;
            default : next_state = A;
        endcase    
    end
    
    assign z = ((state == A) && x) || ((state == B) && !x);
    //always @(posedge clk, posedge areset) 
    //    begin
    //        if(areset) begin
     //           z = 'b0;
     //       end
      //      else begin
      //          case(state)
      //              A : z = x ? 1 : 0;
      //              B : z = x ? 0 : 1;
      //              default : z <= 0;
      //          endcase
      //      end
      //  end
endmodule

Q2:FSM

问题描述

代码

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    reg [3:0]state, next_state;
    parameter A = 'd1, B = 'd2, B1 = 'd3, B2 = 'd4, B3 = 'd5, B4 = 'd6, B5 = 'd7, B6 = 'd8, B7 = 'd9 ;
    always @(posedge clk) begin
        if(reset) begin
            state <= A;
        end
        else begin
            state <= next_state;
        end
    end
    always @(*)
        begin
            case(state) 
                A : next_state  = s ? B : A;
                B : next_state  = w ? B1 : B2;   //1 0
                
                B1 : next_state = w ? B3 : B4; //11 10 
                B2 : next_state = w ? B4 : B5; //01 00
                
                B3 : next_state = w ? B6 : B7; //111 110 
                B4 : next_state = w ? B7 : B6; //101 100
                B5 : next_state = B6; //01
                
                B6 : next_state = w ? B1 : B2; //00
                B7 : next_state = w ? B1 : B2; //00
                default : next_state = A;
            endcase
        end
    assign z = (state == B7);
endmodule

q3b : FSM

问题描述

代码

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
	parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
    reg [2:0] state, next_state;
    always @(posedge clk) begin
        if(reset)
            state <= A;
        else 
            state <= next_state;
    end
    
    always @(*) begin
        case(state)
            A : next_state <= x ? B : A;
            B : next_state <= x ? E : B;
            C : next_state <= x ? B : C;
            D : next_state <= x ? C : B;
            E : next_state <= x ? E : D;
            default : next_state <= A;
        endcase
    end
    
    assign z = (state == E) || (state == D);
    //always @(*) begin
    //    if(reset)
    //        z = 'b0;
    //    else 
     //       z = (state == E) || (state == D);
    //end
endmodule

Q3C: FSM LOGIC

问题描述

代码

module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);
	parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;
    reg [2:0] next_state;
    always @(*) begin
        case(y) 
            A : next_state = x ? B : A;
            B : next_state = x ? E : B;
            C : next_state = x ? B : C;
            D : next_state = x ? C : B;
            E : next_state = x ? E : D;
            default : next_state = A;
        endcase
    end
    assign Y0 = (next_state == B) || (next_state == D); 
    assign z  = (y == D) || (y == E); 
endmodule

Q6b: FSM next-state logic

问题描述

代码

module top_module (
    input [3:1] y,
    input w,
    output Y2);

    parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100, F = 3'b101;
    reg [2:0] next_state;
    always @(*) begin
        case(y) 
            A : next_state = w ? A : B;
            B : next_state = w ? D : C;
            C : next_state = w ? D : E;
            D : next_state = w ? A : F;
            E : next_state = w ? D : E;
            F : next_state = w ? D : C;
            default : next_state = A;
        endcase
    end
    
    assign Y2 = (next_state[1]);
endmodule

Q6C : FSM one-hot next-state logic

问题描述

代码

module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);

  //  parameter A = 6'b000001, B = 6'b000010, C = 6'b000100, D = 6'b001000, E = 6'b010000, F = 6'b100000;
    reg [5:0] next_state;
    always @(*) begin
            next_state[0] = w ? (y[1] || y[4]) : 1'b0;
            next_state[1] = w ? 1'b0 : y[1];
            next_state[2] = w ? 1'b0 : y[2] || y[6];
            next_state[3] = w ? y[2] || y[3] || y[5] || y[6]: 1'b0;
            next_state[4] = w ? 1'b0 : y[3] || y[5];
            next_state[5] = w ? 1'b0 : y[4];
            //default : next_state = A;
    end
    
    assign Y2 = (next_state[1]);
    assign Y4 = (next_state[3]);
endmodule

****独热码

Q6:FSM

问题描述

代码

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);

    parameter A = 'd1, B  = 'd2, C = 'd3, D = 'd4, E = 'd5, F = 'd6;
    reg [2:0]state, next_state;
    always @( posedge clk) begin
        if(reset)
            state <= A;
        else 
            state <= next_state;
    end
    always @(*) begin
        case(state)
            A : next_state = w ? A : B;
            B : next_state = w ? D : C;
            C : next_state = w ? D : E;
            D : next_state = w ? A : F;
            E : next_state = w ? D : E;
            F : next_state = w ? D : C;
            default : next_state = A;
        endcase
    end
    always @( posedge clk) begin
        if(reset)
            z <= 'b0;
        else begin
            case(next_state)
                A : z <= 1'b0;
            	B : z <= 1'b0;
            	C : z <= 1'b0;
            	D : z <= 1'b0;
            	E : z <= 1'b1;
            	F : z <= 1'b1;
            default : z <= 1'b0;
            endcase
        end
    end
endmodule

问题描述

Q2a:FSM

问题描述

代码

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
    reg [3:0] state, next_state;
    parameter A = 4'b0001, B = 4'b0010, C = 4'b0100, D = 4'b1000;
    always @(posedge clk)
        begin
            if(!resetn) begin
                state <= A;
            end
            else begin
               state <= next_state; 
            end
        end
    
    always @(*) begin
        case(state)
            A : next_state <= r[1] ? B : (r[2] ? C : (r[3] ? D : A));
            B : next_state <= r[1] ? B : A;
            C : next_state <= r[2] ? C : A;
            D : next_state <= r[3] ? D : A;
            default : next_state <= A;
        endcase
    end
    always @(posedge clk) begin
        if(!resetn)
            g <= 'b0;
        else begin
        case(next_state)
            B : g[1] <= 1;
            C : g[2] <= 1;
            D : g[3] <= 1;
            default : g <= 3'b0;
        endcase
        end
    end
endmodule

Q2b: another FSM

问题描述

代码

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter A = 4'd1, F = 4'd2 , X = 4'd3 , X1 = 4'd4 , X10 = 4'd5, X101 = 4'd6, Y0 = 4'd7, Y1 = 4'd8, Y00 = 4'd9;
    reg [3:0] state, next_state;
    always @(posedge clk) begin
        if(!resetn)
            state <= A;
        else 
            state <= next_state;
    end
    always @(*) begin
        case(state) 
            A 	 : next_state = resetn ? F : A; //f out 1  
            F 	 : next_state = X; 				//judge x
            X    : next_state = x ? X1 : X; 	// value y
            X1   : next_state = x ? X1 :X10;
            X10  : next_state = x ? X101 :X;
            X101 : next_state = y ? Y1 : Y0;
            Y0   : next_state = y ? Y1 : Y00;
            Y1   : next_state =  Y1;
            Y00   : next_state =  Y00;
            default : ;
        endcase
    end
    always @(posedge clk) begin
        if(!resetn) begin
            f <= 1'b0;
            g <= 1'b0;
        end
        else begin
        case(next_state) 
            F : begin 
                f <= 1'b1;
            	g <= 1'b0;
            end
            X :begin 
                f <= 1'b0;
            	g <= 1'b0;
            end
            X101 :begin 
            	g <= 1'b1;
            end
           	Y00 :begin 
            	g <= 1'b0;
                
            end
        endcase
        end
    end     
            
endmodule

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