Fsm1\Fsm2_HDLbits(状态机入门四道Verilog例题)

状态机：有限状态机（Finite State Machine）,

(1)若输出只和状态有关而与输入无关，则称为Moore状态机

 (2)输出不仅和状态有关而且和输入有关系，则称为Mealy状态机

1、This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.（This is a TFF with the T input inverted.）

（异步areset）

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        if(state==A)  next_state <= in? state:B;
              
        if(state==B)   next_state <= in? state:A; 
    end
//状态变化关系这一部分一开始写成了 if(in) next_state<=B;，没有考虑到当in=1时。次态应该等于state，关系没有捋清楚。

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset) state<=B;
        else state<=next_state;
        
    end
    assign out=(state==B)?1:0;

    // Output logic
    // assign out = (state == ...);

endmodule

2、This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

（状态变换同上，同步reset）

 

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations

    reg present_state, next_state;
	parameter A=0, B=1;
 
    always @(posedge clk) 
        begin
        //状态变换逻辑用阻塞赋值,一开始下意识的用非阻塞，这样导致循环结束后才进行值的传递。
        //而输出是在循环中的，导致输出值不匹配。例如，当reset为1时，<=使得在循环结束后才将B赋值给next_state,
        //这导致在触发时present_state的值在循环结束前保持上次循环结束时的值，从而在out的判断上产生误判。
            if (reset) begin  next_state = B;  end
                // Fill in reset logic 
            else  begin
                case (present_state)
                    A:next_state =(in)? present_state:B;
                    B:next_state =(in)? present_state:A;
                    // Fill in state transition logic
                endcase
            end  
        //原题中else的end位置错误，一开始没注意找了半天。
            // State flip-flops
            present_state = next_state;   
        //次态和当前态的转换也需要用阻塞赋值。
        
            case (present_state)
                A:	out <= 0;
                B:	out <= 1;
        //输出这一部分不影响
                // Fill in output logic
            endcase
       
        end

endmodule

 3、This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.(This is a JK flip-flop.)

异步areset

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) 
        begin
            if(state==ON) next_state<=(k)? OFF:state;
            if(state==OFF) next_state<=(j)? ON:state;
        // State transition logic
    	end

    always @(posedge clk, posedge areset) //和后一题的差别就在敏感信号这里
        begin
            if(areset) state<=OFF;
            else 
                state<=next_state;
        // State flip-flops with asynchronous reset
    	end
    assign out = (state==ON)? 1:0;
    // Output logic
    // assign out = (state == ...);

endmodule

 4、This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.(This is a JK flip-flop.)

 同步areset

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) 
        begin
        	if(state==ON) next_state<=(k)? OFF:state;
            if(state==OFF) next_state<=(j)? ON:state;
        // State transition logic
    end

    always @(posedge clk)
        begin
             if(reset) state<=OFF;
             else state<=next_state;
        // State flip-flops with asynchronous reset
    	end
	assign out = (state==ON)? 1:0;
    // Output logic
    // assign out = (state == ...);

endmodule