Reference code
/**
* cvmx_cpri#_bfn
*/
union cvmx_cprix_bfn {
uint64_t u64;
struct cvmx_cprix_bfn_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t bfn : 12; /**< Current BFN from BFN alignment state machine. */
#else
uint64_t bfn : 12;
uint64_t reserved_12_63 : 52;
#endif
} s;
struct cvmx_cprix_bfn_s cnf75xx;
};
typedef union cvmx_cprix_bfn cvmx_cprix_bfn_t;
/**
* cvmx_cpri#_cm_config
*/
union cvmx_cprix_cm_config {
uint64_t u64;
struct cvmx_cprix_cm_config_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63 : 53;
uint64_t tx_slow_cm_rate : 3; /**< Reserved. CNF75XX does not support HDLC. */
uint64_t reserved_6_7 : 2;
uint64_t tx_fast_cm_ptr : 6; /**< Pointer to first CPRI control word used for fast C&M. This value will be inserted into
CPRI
control byte Z.194.0. */
#else
uint64_t tx_fast_cm_ptr : 6;
uint64_t reserved_6_7 : 2;
uint64_t tx_slow_cm_rate : 3;
uint64_t reserved_11_63 : 53;
#endif
} s;
struct cvmx_cprix_cm_config_s cnf75xx;
};
typedef union cvmx_cprix_cm_config cvmx_cprix_cm_config_t;
/**
* cvmx_cpri#_cm_status
*
* This register reports the received C&M channel configuration.
*
*/
union cvmx_cprix_cm_status {
uint64_t u64;
struct cvmx_cprix_cm_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t rx_slow_cm_rate_valid : 1; /**< When set, indicates that a valid slow C&M rate has been accepted. Note
that slow C&M channel is not supported and recevied data will be
discarded. */
uint64_t rx_slow_cm_rate : 3; /**< Accepted receive slow C&M rate.
0x0 = No HDLC.
0x1 = 240 Kbit/s.
0x2 = 480 Kbit/s.
0x3 = 960 Kbit/s.
0x4 = 1920 Kbit/s.
0x5 = 2400 Kbit/s.
0x6 = Highest possible rate when line rate is greater than 3072 Mbps.
0x7 = Reserved. */
uint64_t reserved_7_7 : 1;
uint64_t rx_fast_cm_ptr_valid : 1; /**< When set, indicates that a valid fast C&M pointer has been accepted. */
uint64_t rx_fast_cm_ptr : 6; /**< Accepted receive fast C&M pointer. */
#else
uint64_t rx_fast_cm_ptr : 6;
uint64_t rx_fast_cm_ptr_valid : 1;
uint64_t reserved_7_7 : 1;
uint64_t rx_slow_cm_rate : 3;
uint64_t rx_slow_cm_rate_valid : 1;
uint64_t reserved_12_63 : 52;
#endif
} s;
struct cvmx_cprix_cm_status_s cnf75xx;
};
typedef union cvmx_cprix_cm_status cvmx_cprix_cm_status_t;
/**
* cvmx_cpri#_config
*/
union cvmx_cprix_config {
uint64_t u64;
struct cvmx_cprix_config_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t ori_spec : 1; /**< ORI specification version used for RTWP mapping.
0 = ORI spec version 1.1.1.
1 = ORI spec version 4.1.1. */
uint64_t set_10_acks : 1; /**< N/A */
uint64_t rtwp_enable_rx : 1; /**< When set, enables extraction of RTWP. */
uint64_t rtwp_enable_tx : 1; /**< N/A */
uint64_t cnt_6_reset : 1; /**< N/A */
uint64_t sync_pulse_in_re_mode : 1; /**< N/A */
uint64_t rx_enable_buffer : 1; /**< 0 = Disable CPRI receiver.
1 = Enable CPRI receiver. */
uint64_t ethernet_idle_select : 1; /**< Select whether to transmit zeros or ones on Ethernet channel when
idle. This only applies when [ETHERNET_MODE] = 1.
0 = Transmit zeros when idle.
1 = Transmit ones when idle. */
uint64_t rx_cm_select : 1; /**< Receiver control and management (C & M) channel configuration.
0 = Use accepted values.
1 = Use TX configuration. */
uint64_t ethernet_mode : 1; /**< Select mapping of Fast C&M Ethernet channel.
0 = Standard CPRI v.4.2 mode.
1 = Alternative IR mapping mode. */
uint64_t tx_enable : 1; /**< 0 = Disable transmit operations.
1 = Enable transmit operations. */
uint64_t loop_mode : 3; /**< N/A */
uint64_t sync_mode : 1; /**< N/A */
uint64_t tx_ctrl_insert_en : 1; /**< Global enable on CPRI control word insertion. This bit overrides the
insertion enables configured using the CPRI()_TX_CTRL register. When
[TX_CTRL_INSER_EN] is set to one, individual bytes must also be enabled
using CPRI()_TX_CTRL regiser. When cleared, none of the control words
specified by CPRI()_TX_CTRL are inserted in the transmitted frames. */
#else
uint64_t tx_ctrl_insert_en : 1;
uint64_t sync_mode : 1;
uint64_t loop_mode : 3;
uint64_t tx_enable : 1;
uint64_t ethernet_mode : 1;
uint64_t rx_cm_select : 1;
uint64_t ethernet_idle_select : 1;
uint64_t rx_enable_buffer : 1;
uint64_t sync_pulse_in_re_mode : 1;
uint64_t cnt_6_reset : 1;
uint64_t rtwp_enable_tx : 1;
uint64_t rtwp_enable_rx : 1;
uint64_t set_10_acks : 1;
uint64_t ori_spec : 1;
uint64_t reserved_16_63 : 48;
#endif
} s;
struct cvmx_cprix_config_s cnf75xx;
};
typedef union cvmx_cprix_config cvmx_cprix_config_t;
/**
* cvmx_cpri#_ctrl_index
*
* This register selects which control word will be read/written by accesses
* to both the CPRI()_RX_CTRL and CPRI()_TX_CTRL registers.
*/
union cvmx_cprix_ctrl_index {
uint64_t u64;
struct cvmx_cprix_ctrl_index_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63 : 52;
uint64_t cpri_ctrl_sel : 4; /**< Specifies the byte y within the control word Z.x.0. */
uint64_t cpri_ctrl_indx : 8; /**< Specifies the basic frame index 'x' for the control word Z.x.0. */
#else
uint64_t cpri_ctrl_indx : 8;
uint64_t cpri_ctrl_sel : 4;
uint64_t reserved_12_63 : 52;
#endif
} s;
struct cvmx_cprix_ctrl_index_s cnf75xx;
};
typedef union cvmx_cprix_ctrl_index cvmx_cprix_ctrl_index_t;
/**
* cvmx_cpri#_eth_addr_lsb
*/
union cvmx_cprix_eth_addr_lsb {
uint64_t u64;
struct cvmx_cprix_eth_addr_lsb_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t mac_31_0 : 32; /**< Least signficant four bytes of local MAC address. */
#else
uint64_t mac_31_0 : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_cprix_eth_addr_lsb_s cnf75xx;
};
typedef union cvmx_cprix_eth_addr_lsb cvmx_cprix_eth_addr_lsb_t;
/**
* cvmx_cpri#_eth_addr_msb
*
* Ethernet MAC address (MSB)
*
*/
union cvmx_cprix_eth_addr_msb {
uint64_t u64;
struct cvmx_cprix_eth_addr_msb_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63 : 48;
uint64_t mac_47_32 : 16; /**< Most significant two bytes of local MAC address. */
#else
uint64_t mac_47_32 : 16;
uint64_t reserved_16_63 : 48;
#endif
} s;
struct cvmx_cprix_eth_addr_msb_s cnf75xx;
};
typedef union cvmx_cprix_eth_addr_msb cvmx_cprix_eth_addr_msb_t;
/**
* cvmx_cpri#_eth_cnt_dmac_mism
*/
union cvmx_cprix_eth_cnt_dmac_mism {
uint64_t u64;
struct cvmx_cprix_eth_cnt_dmac_mism_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t eth_cnt_dmac_mismatch : 32; /**< The number of received (and discarded) frames whose destination MAC
address did not match the local MAC address and didn't pass the
multicast or broadcast filters. */
#else
uint64_t eth_cnt_dmac_mismatch : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_cprix_eth_cnt_dmac_mism_s cnf75xx;
};
typedef union cvmx_cprix_eth_cnt_dmac_mism cvmx_cprix_eth_cnt_dmac_mism_t;
/**
* cvmx_cpri#_eth_cnt_rx_frame
*/
union cvmx_cprix_eth_cnt_rx_frame {
uint64_t u64;
struct cvmx_cprix_eth_cnt_rx_frame_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t eth_cnt_rx_frame : 32; /**< Number of received frames. */
#else
uint64_t eth_cnt_rx_frame : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_cprix_eth_cnt_rx_frame_s cnf75xx;
};
typedef union cvmx_cprix_eth_cnt_rx_frame cvmx_cprix_eth_cnt_rx_frame_t;
/**
* cvmx_cpri#_eth_cnt_tx_frame
*/
union cvmx_cprix_eth_cnt_tx_frame {
uint64_t u64;
struct cvmx_cprix_eth_cnt_tx_frame_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t eth_cnt_tx_frame : 32; /**< Number of transmitted frames. */
#else
uint64_t eth_cnt_tx_frame : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_cprix_eth_cnt_tx_frame_s cnf75xx;
};
typedef union cvmx_cprix_eth_cnt_tx_frame cvmx_cprix_eth_cnt_tx_frame_t;
/**
* cvmx_cpri#_eth_config_1
*
* Ethernet configuration
*
*/
union cvmx_cprix_eth_config_1 {
uint64_t u64;
struct cvmx_cprix_eth_config_1_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_22_63 : 42;
uint64_t crc_strip_en : 1; /**< When set, the CRC is stripped from incoming packets. */
uint64_t mac_fail_pass_en : 1; /**< Accept incoming packets that fail the unicast, multicast and broadcast
MAC checks.
0 = When [MAC_CHECK]=1, packets not passing any filter are discarded.
1 = When [MAC_CHECK]=1, packets that do not pass any filters are
accepted, and the failure is recorded by setting
RFIF_ETH_RX_WQE_S[DMAC_MISMATCH]=1 and
RFIF_ETH_RX_WQE_S[MAC_RES]=0x7. */
uint64_t intr_tx_ready_block_en : 1; /**< N/A */
uint64_t intr_tx_abort_en : 1; /**< N/A */
uint64_t intr_tx_ready_en : 1; /**< N/A */
uint64_t intr_rx_ready_block_en : 1; /**< N/A */
uint64_t intr_rx_ready_end_en : 1; /**< N/A */
uint64_t intr_rx_abort_en : 1; /**< N/A */
uint64_t intr_rx_ready_en : 1; /**< N/A */
uint64_t intr_tx_en : 1; /**< N/A */
uint64_t intr_rx_en : 1; /**< N/A */
uint64_t intr_en : 1; /**< N/A */
uint64_t rx_long_frame_en : 1; /**< When set, enable reception of Ethernet frame longer than 1536 bytes.
Note that the RFIF RMAC does not support Ethernet frames longer than
1536 bytes. */
uint64_t rx_preamble_abort_en : 1; /**< When set, discard incoming frames with illegal preamble nibble for
receiving SFD. */
uint64_t broadcast_en : 1; /**< When [MAC_CHECK]=1, allow incoming broadcast packets. */
uint64_t multicast_flt_en : 1; /**< When [MAC_CHECK]=1, enable the multicast filter. Refer to
CPRI()_ETH_HASH_TABLE for more details. */
uint64_t mac_check : 1; /**< When set, enable checking of the destination MAC address for received
packets.
When MAC_CHECK=1, packets with the DMAC set to the local MAC address
will be accepted. If [MULTICAST_FLT_EN]=1, then multicast packets that
are accepted by the mutlicast filter are also accepted. If
[BROADCAST_EN]=1, then broadcast packets are also accepted. All other
packets are discarded. */
uint64_t length_check : 1; /**< When set, packets smaller than 64 bytes will be discarded. */
uint64_t mac_reset : 1; /**< Ethernet MAC reset. */
uint64_t reserved_2_2 : 1;
uint64_t little_endian_en : 1; /**< Select the endianness for Ethernet receive and transmit data:
0 = Big-endian.
1 = Little-endian. */
uint64_t reserved_0_0 : 1;
#else
uint64_t reserved_0_0 : 1;
uint64_t little_endian_en : 1;
uint64_t reserved_2_2 : 1;
uint64_t mac_reset : 1;
uint64_t length_check : 1;
uint64_t mac_check : 1;
uint64_t multicast_flt_en : 1;
uint64_t broadcast_en : 1;
uint64_t rx_preamble_abort_en : 1;
uint64_t rx_long_frame_en : 1;
uint64_t intr_en : 1;
uint64_t intr_rx_en : 1;
uint64_t intr_tx_en : 1;
uint64_t intr_rx_ready_en : 1;
uint64_t intr_rx_abort_en : 1;
uint64_t intr_rx_ready_end_en : 1;
uint64_t intr_rx_ready_block_en : 1;
uint64_t intr_tx_ready_en : 1;
uint64_t intr_tx_abort_en : 1;
uint64_t intr_tx_ready_block_en : 1;
uint64_t mac_fail_pass_en : 1;
uint64_t crc_strip_en : 1;
uint64_t reserved_22_63 : 42;
#endif
} s;
struct cvmx_cprix_eth_config_1_s cnf75xx;
};
typedef union cvmx_cprix_eth_config_1 cvmx_cprix_eth_config_1_t;
/**
* cvmx_cpri#_eth_config_2
*/
union cvmx_cprix_eth_config_2 {
uint64_t u64;
struct cvmx_cprix_eth_config_2_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t crc_enable : 1; /**< When set, enable automatic insertion of Ethernet FCS at the end of
each frame. When cleared, software must include the FCS in each frame.
Note that when including the FCS manually, the bit order must be
reversed for the FCS bytes. */
#else
uint64_t crc_enable : 1;
uint64_t reserved_1_63 : 63;
#endif
} s;
struct cvmx_cprix_eth_config_2_s cnf75xx;
};
typedef union cvmx_cprix_eth_config_2 cvmx_cprix_eth_config_2_t;
/**
* cvmx_cpri#_eth_config_3
*/
union cvmx_cprix_eth_config_3 {
uint64_t u64;
struct cvmx_cprix_eth_config_3_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63 : 50;
uint64_t tx_start_thr : 6; /**< Transmit start threshold. When store-and-forward mode is not enabled, transmission
will start when the specified number of 32-bit words have been stored in the
transmit buffer. */
uint64_t reserved_2_7 : 6;
uint64_t rx_crc_en : 1; /**< When set, enables FCS validation of received packets (packets that
fail the check are discarded). When cleared, no validation is
performed and all packets are accepted. */
uint64_t tx_st_fwd : 1; /**< Select between store-and-forward and cut-through mode.
0 = Cut-through mode. Transmission stars when the buffer fill-level
exceeds [TX_START_THR].
1 = Store-and-forward mode. Store a full packet before start of
transmission. Packets longer than transmit buffer (256 bytes) will be aborted. */
#else
uint64_t tx_st_fwd : 1;
uint64_t rx_crc_en : 1;
uint64_t reserved_2_7 : 6;
uint64_t tx_start_thr : 6;
uint64_t reserved_14_63 : 50;
#endif
} s;
struct cvmx_cprix_eth_config_3_s cnf75xx;
};
typedef union cvmx_cprix_eth_config_3 cvmx_cprix_eth_config_3_t;
/**
* cvmx_cpri#_eth_hash_table
*
* This register configures the multicast filter hash table.
*
* When CPRI()_ETH_CONFIG_1[MAC_CHECK]=1 and
* CPRI()_ETH_CONFIG_1[MULIT_CAST_FLT_EN]=1, received multicast packets are
* filtered based on this hash table. Multicast packets must have bit 0 of
* the least significant byte in the DMAC set to 1. The Ethernet CRC function
* is then applied to the DMAC address, and the CRC value is used to select
* one bit from [HASH]. If that bit is set, then the multicast packet is
* accepted, otherwise the multicast packet is discarded.
*/
union cvmx_cprix_eth_hash_table {
uint64_t u64;
struct cvmx_cprix_eth_hash_table_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t hash : 32; /**< When bit i is set, then multicast DMAC addresses with a CRC of i
are accepted by the filter. If the bit is cleared, matching DMAC
addresses are discarded. */
#else
uint64_t hash : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_cprix_eth_hash_table_s cnf75xx;
};
typedef union cvmx_cprix_eth_hash_table cvmx_cprix_eth_hash_table_t;
/**
* cvmx_cpri#_eth_rx_control
*
* Ethernet receive control
*
*/
union cvmx_cprix_eth_rx_control {
uint64_t u64;
struct cvmx_cprix_eth_rx_control_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63 : 63;
uint64_t rx_discard : 1; /**< 1 = Discard current Ethernet RX frame.
0 = Discard not enabled. */
#else
uint64_t rx_discard : 1;
uint64_t reserved_1_63 : 63;
#endif
} s;
struct cvmx_cprix_eth_rx_control_s cnf75xx;
};
typedef union cvmx_cprix_eth_rx_control cvmx_cprix_eth_rx_control_t;
/**
* cvmx_cpri#_eth_rx_data
*
* Ethernet receive data
*
*/
union cvmx_cprix_eth_rx_data {
uint64_t u64;
struct cvmx_cprix_eth_rx_data_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t rx_data : 32; /**< Ethernet RX frame data. */
#else
uint64_t rx_data : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
struct cvmx_cprix_eth_rx_data_s cnf75xx;
};
typedef union cvmx_cprix_eth_rx_data cvmx_cprix_eth_rx_data_t;
/**
* cvmx_cpri#_eth_rx_data_wait
*
* Ethernet receive data with wait-state
*
*/
union cvmx_cprix_eth_rx_data_wait {
uint64_t u64;
struct cvmx_cprix_eth_rx_data_wait_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63 : 32;
uint64_t rx_data : 32; /**< Ethernet RX frame data.Wait states will be inserted until data is ready (or
the CPU time-out the operation). */
#else
uint64_t rx_data : 32;
uint64_t reserved_32_63 : 32;
#endif
} s;
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