FPGA Verilog IIC控制EEPROM

最新推荐文章于 2023-08-12 15:47:48 发布

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最新推荐文章于 2023-08-12 15:47:48 发布

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IIC通信协议简介

IIC只有两根线，一根SDA数据线，一根SCL数据线。
1、除了开始标志和结束标志，其余时间不允许在时钟信号高电平时数据线信号产生变化。因此写数据需要在时钟低电平时写入，读数据要在时钟高电平时读出。
2、开始和结束标志：在时钟线为高电平时，数据线电平由高变低（开始），数据线电平由低变高（结束）。
3、主机每发送8位数据，从机都会回应一位低电平的ACK信号。

EEPROM读写操作的流程

在进行写操作时，先写入从机地址（每个器件的从机地址都是固定的）以及读写标志位，再写入数据地址（有的是8位有的是16位），再写入数据。在进行随机读操作（即读取任意地址的数据）时，需要先进行一次哑写操作，写入要读取的地址。详见https://ww1.microchip.com/downloads/en/DeviceDoc/doc0336.pdf
图片来源于正点原子

module iic_ctrl(
input wire sys_clk,//系统时钟
input wire sys_rst,//系统复位
input wire [7:0] i2c_data_w,//输入数据
input wire [15:0] i2c_adrr,//输入地址
input wire  i2c_exec   ,//i2c开始信号
input wire bit_ctrl,//为1时代表地址16位，为0时代表地址8位。
input wire write_flag,//写标志
output reg [7:0] i2c_data_r,//读出的数据
output reg i2c_done,//i2c操作完成标志
output reg i2c_ack,//i2c从机应答信号
output reg i2c_clk,//i2c控制时钟
output reg SCL,//i2c时钟
inout  wire SDA//i2c数据线
);
parameter   SLAVE_ADDR = 7'b1010000   ;  //EEPROM从机地址
parameter   CLK_FREQ   = 26'd50_000_000; //模块输入的时钟频率
parameter   I2C_FREQ   = 18'd250_000    ; //IIC_SCL的时钟频率
parameter i2c_scl_cnt_max=((CLK_FREQ/I2C_FREQ)>>3);//生成i2c控制时钟
reg [8:0]i2c_scl_cnt;//控制时钟计数器
//状态机定义
localparam st_idle =8'b0000_0001;
localparam st_sladdr =8'b0000_0010;
localparam st_adder16=8'b0000_0100;
localparam st_adder8=8'b0000_1000;
localparam st_writ_data=8'b0001_0000;
localparam st_read_adder=8'b0010_0000;
localparam st_read_data=8'b0100_0000;
localparam st_stop=8'b1000_0000;
reg [7:0] state,next_state;

reg st_done;//状态机状态转换信号
//将输入信号寄存起来
reg [7:0] data_to_write;
reg [7:0] data_to_read;
reg [15:0] adder_to_write;
reg bit_8or16;
reg [5:0] cnt;//计数控制时钟周期
reg sdr;//三态门控制信号
reg SDA_OUT;
wire SDA_IN;
//三态门定义
assign SDA=sdr?SDA_OUT:1'bz;
assign SDA_IN=sdr?1'bz:SDA;


always@(posedge sys_clk or negedge sys_rst)
if(!sys_rst)
begin
i2c_scl_cnt<=0;
i2c_clk<=0;
end
else if(i2c_scl_cnt==i2c_scl_cnt_max-1'b1)
begin
i2c_scl_cnt<=0;
i2c_clk=~i2c_clk;
end
else
i2c_scl_cnt<=i2c_scl_cnt+1'b1;

//状态机第二段注意使用的时钟
always@(posedge i2c_clk or negedge sys_rst)
    if(!sys_rst)
    state<=st_idle;
    else
    state<=next_state;

//状态机第一段
always@(*)
begin
    case(state)
    st_idle:next_state=i2c_exec?st_sladdr:st_idle;
    st_sladdr:begin
            if(st_done)
               begin
                if(bit_8or16)
                   next_state=st_adder16;
                else
                    next_state=st_adder8;
                end
            else
                next_state=st_sladdr;
            end
            
    st_adder16:next_state=st_done?st_adder8:st_adder16;
    
    st_adder8:begin 
              if(st_done)
               begin
                 if(!write_flag)
                     next_state=st_writ_data;
                 else
                     next_state=st_read_adder;
                 end
              else
                 next_state=st_adder8;
            end
            
    st_writ_data:next_state=st_done?st_stop:st_writ_data;

    st_read_adder:next_state=st_done?st_read_data:st_read_adder;

    st_read_data:next_state=st_done?st_stop:st_read_adder;

    st_stop:next_state=st_done?st_idle:st_stop;

    default: ;

   endcase
end

always@(posedge i2c_clk or negedge sys_rst)
if(!sys_rst)
begin
SCL=1'b1;
i2c_ack=1'b0;
i2c_done=1'b0;
st_done=1'b0;
cnt<=1'b0;
data_to_read<=1'b0;
data_to_write<=1'b0;
adder_to_write<=1'b0;
bit_8or16<=0;
SDA_OUT<=1;
sdr<=1;
end 
else begin
cnt<=cnt+1'b1;//随着上升沿到来累加
st_done <= 1'b0 ; 
case (state)
//将输入信号寄存
st_idle:if(next_state==st_sladdr)
begin
bit_8or16<=bit_ctrl;
data_to_write<=i2c_data_w;
adder_to_write<=i2c_adrr;
cnt<=0;
end
//写入从机地址
st_sladdr:begin
case(cnt)
7'd0:sdr<=1;
7'd1:SDA_OUT<=1'b0;//开始标志

7'd2:SCL<=1'b0;
7'd3:SDA_OUT<=SLAVE_ADDR[6];
7'd4:SCL<=1'b1;

7'd6:SCL<=1'b0;
7'd7:SDA_OUT<=SLAVE_ADDR[5];
7'd8:SCL<=1'b1;

7'd10:SCL<=1'b0;
7'd11:SDA_OUT<=SLAVE_ADDR[4];
7'd12:SCL<=1'b1;

7'd14:SCL<=1'b0;
7'd15:SDA_OUT<=SLAVE_ADDR[3];
7'd16:SCL<=1'b1;

7'd18:SCL<=1'b0;
7'd19:SDA_OUT<=SLAVE_ADDR[2];
7'd20:SCL<=1'b1;

7'd22:SCL<=1'b0;
7'd23:SDA_OUT<=SLAVE_ADDR[1];
7'd24:SCL<=1'b1;

7'd26:SCL<=1'b0;
7'd27:SDA_OUT<=SLAVE_ADDR[0];
7'd28:SCL<=1'b1;

7'd30:SCL<=1'b0;
7'd31:SDA_OUT<=1'b0;//写
7'd32:SCL<=1'b1;

7'd34: SCL<=1'b0;

7'd35: sdr<=1'b0;//三态门切换到输入状态
                 
7'd36:SCL<=1'b1;

7'd37:begin  
        i2c_ack=SDA_IN?1'b1:1'b0;//是否收到从机应答
        st_done<=1'b1;//状态结束标志
      end
7'd38:begin 
        SCL<=1'b0;
        cnt<=1'b0;//计数器清零
            
      end
default  : ;
endcase
end
//写入数据地址的高八位
st_adder16:begin
case(cnt)
7'd0: begin
      sdr<=1'b1;
      SDA_OUT<=adder_to_write[15];
      end
7'd1:SCL<=1'b1;

7'd3:SCL<=1'b0;
7'd4:SDA_OUT<=adder_to_write[14];
7'd5:SCL<=1'b1;

7'd7:SCL<=1'b0;
7'd8:SDA_OUT<=adder_to_write[13];
7'd9:SCL<=1'b1;

7'd11:SCL<=1'b0;
7'd12:SDA_OUT<=adder_to_write[12];
7'd13:SCL<=1'b1;

7'd15:SCL<=1'b0;
7'd16:SDA_OUT<=adder_to_write[11];
7'd17:SCL<=1'b1;

7'd19:SCL<=1'b0;
7'd20:SDA_OUT<=adder_to_write[10];
7'd21:SCL<=1'b1;

7'd23:SCL<=1'b0;
7'd24:SDA_OUT<=adder_to_write[9];
7'd25:SCL<=1'b1;

7'd27:SCL<=1'b0;
7'd28:SDA_OUT<=adder_to_write[8];
7'd29:SCL<=1'b1;

7'd31:SCL<=1'b0;
7'd32:sdr<=1'b0;
7'd33:SCL<=1'b1;

7'd34:begin 
        i2c_ack=SDA_IN?1'b1:1'b0;
        st_done<=1'b1;
      end
7'd35:begin SCL<=1'b0;
            
            cnt<=1'b0;
            end       
 default  : ;
endcase
end
//写入地址低八位
st_adder8:begin
case(cnt)
7'd0:begin
     sdr<=1'b1; 
     SDA_OUT<=adder_to_write[7];
     end
7'd1:SCL<=1'b1;

7'd3:SCL<=1'b0;
7'd4:SDA_OUT<=adder_to_write[6];
7'd5:SCL<=1'b1;

7'd7:SCL<=1'b0;
7'd8:SDA_OUT<=adder_to_write[5];
7'd9:SCL<=1'b1;

7'd11:SCL<=1'b0;
7'd12:SDA_OUT<=adder_to_write[4];
7'd13:SCL<=1'b1;

7'd15:SCL<=1'b0;
7'd16:SDA_OUT<=adder_to_write[3];
7'd17:SCL<=1'b1;

7'd19:SCL<=1'b0;
7'd20:SDA_OUT<=adder_to_write[2];
7'd21:SCL<=1'b1;

7'd23:SCL<=1'b0;
7'd24:SDA_OUT<=adder_to_write[1];
7'd25:SCL<=1'b1;

7'd27:SCL<=1'b0;
7'd28:SDA_OUT<=adder_to_write[0];
7'd29:SCL<=1'b1;

7'd31:SCL<=1'b0;
7'd32:sdr<=1'b0;
7'd33:SCL<=1'b1;

7'd34:begin i2c_ack=SDA_IN?1'b1:1'b0;
            st_done<=1'b1;
end
7'd35:begin SCL<=1'b0;
            
            cnt<=1'b0;
            end       
 default  : ;
endcase
end
//写入数据            
st_writ_data:begin
case(cnt)
7'd0: 
begin
SDA_OUT<=data_to_write[7];
sdr<=1'b1;
end
7'd1:SCL<=1'b1;

7'd3:SCL<=1'b0;
7'd4:SDA_OUT<=data_to_write[6];
7'd5:SCL<=1'b1;

7'd7:SCL<=1'b0;
7'd8:SDA_OUT<=data_to_write[5];
7'd9:SCL<=1'b1;

7'd11:SCL<=1'b0;
7'd12:SDA_OUT<=data_to_write[4];
7'd13:SCL<=1'b1;

7'd15:SCL<=1'b0;
7'd16:SDA_OUT<=data_to_write[3];
7'd17:SCL<=1'b1;

7'd19:SCL<=1'b0;
7'd20:SDA_OUT<=data_to_write[2];
7'd21:SCL<=1'b1;

7'd23:SCL<=1'b0;
7'd24:SDA_OUT<=data_to_write[1];
7'd25:SCL<=1'b1;

7'd27:SCL<=1'b0;
7'd28:SDA_OUT<=data_to_write[0];
7'd29:SCL<=1'b1;

7'd31:SCL<=1'b0;
7'd32:sdr<=1'b0;
7'd33:SCL<=1'b1;

7'd34:begin i2c_ack=SDA_IN?1'b1:1'b0;
            st_done<=1'b1;
end
7'd35:begin SCL<=1'b0;
            
            cnt<=1'b0;
  end 
 default  : ; 
endcase
end
//读数据，要再次写入从机地址
st_read_adder:begin
case(cnt)
7'd1:
begin
SDA_OUT<=1'b0;//开始标志
sdr<=1'b1;
end

7'd2:SCL<=1'b0;
7'd3:SDA_OUT<=SLAVE_ADDR[6];
7'd4:SCL<=1'b1;

7'd6:SCL<=1'b0;
7'd7:SDA_OUT<=SLAVE_ADDR[5];
7'd8:SCL<=1'b1;

7'd10:SCL<=1'b0;
7'd11:SDA_OUT<=SLAVE_ADDR[4];
7'd12:SCL<=1'b1;

7'd14:SCL<=1'b0;
7'd15:SDA_OUT<=SLAVE_ADDR[3];
7'd16:SCL<=1'b1;

7'd18:SCL<=1'b0;
7'd19:SDA_OUT<=SLAVE_ADDR[2];
7'd20:SCL<=1'b1;

7'd22:SCL<=1'b0;
7'd23:SDA_OUT<=SLAVE_ADDR[1];
7'd24:SCL<=1'b1;

7'd26:SCL<=1'b0;
7'd27:SDA_OUT<=SLAVE_ADDR[0];
7'd28:SCL<=1'b1;

7'd30:SCL<=1'b0;
7'd31:SDA_OUT<=1'b1;//读
7'd32:SCL<=1'b1;

7'd34: SCL<=1'b0;

7'd35: sdr<=1'b0;
                 
7'd36:SCL<=1'b1;

7'd37:begin  i2c_ack=SDA_IN?1'b1:1'b0;
      st_done<=1'b1;
      end
7'd38:begin SCL<=1'b0;
            cnt<=1'b0;
           
            end
 default  : ;
endcase
end
//读出数据操作，在时钟为高电平时读取
st_read_data:begin
case(cnt)
//7'd0: SDA_OUT<=data_to_read[7];
7'd1:SCL<=1'b1;
7'd2:data_to_read[7]<=SDA_IN;
7'd3:SCL<=1'b0;

7'd5:SCL<=1'b1;
7'd6:data_to_read[6]<=SDA_IN;
7'd7:SCL<=1'b0;

7'd9:SCL<=1'b1;
7'd10:data_to_read[5]<=SDA_IN;
7'd11:SCL<=1'b0;

7'd13:SCL<=1'b1;
7'd14:data_to_read[4]<=SDA_IN;
7'd15:SCL<=1'b0;

7'd17:SCL<=1'b1;
7'd18:data_to_read[3]<=SDA_IN;
7'd19:SCL<=1'b0;

7'd21:SCL<=1'b1;
7'd22:data_to_read[2]<=SDA_IN;
7'd23:SCL<=1'b0;

7'd25:SCL<=1'b1;
7'd26:data_to_read[1]<=SDA_IN;
7'd27:SCL<=1'b0;

7'd29:SCL<=1'b1;
7'd30:data_to_read[0]<=SDA_IN;
7'd31:SCL<=1'b0;

7'd32:sdr<=1'b0;
7'd33:SCL<=1'b1;

7'd34:st_done<=1'b1;
7'd35:begin SCL<=1'b0;
            sdr<=1'b1;
            cnt<=1'b0;
            i2c_data_r<=data_to_read;
            end  
 default  : ;            
endcase
end
//结束i2c
st_stop: begin                           
case(cnt)
7'd0: begin
    sdr <= 1'b1;             
    SDA_OUT <= 1'b0;//结束标志
end
7'd1 : SCL     <= 1'b1;
7'd3 : SDA_OUT <= 1'b1;
7'd15: st_done <= 1'b1;
7'd16: begin
        cnt      <= 1'b0;
        i2c_done <= 1'b1;  //向上层模块传递I2C结束信号
       end
default  : ;
endcase
end

endcase
            
end

endmodule


//EEPROM_AT24C64的模拟模块（网上找的）
`timescale 1ns/1ns
`define timeslice 1250
module EEPROM_AT24C64(
scl,
sda
);
input scl; 
inout sda; 
reg out_flag; 
reg[7:0] memory[8191:0]; 
reg[12:0]address; 
reg[7:0]memory_buf; 
reg[7:0]sda_buf; 
reg[7:0]shift; 
reg[7:0]addr_byte_h; 
reg[7:0]addr_byte_l; 
reg[7:0]ctrl_byte; 
reg[1:0]State;
integer i;
//---------------------------
parameter
r7 = 8'b1010_1111, w7 = 8'b1010_1110, //main7
r6 = 8'b1010_1101, w6 = 8'b1010_1100, //main6
r5 = 8'b1010_1011, w5 = 8'b1010_1010, //main5
r4 = 8'b1010_1001, w4 = 8'b1010_1000, //main4
r3 = 8'b1010_0111, w3 = 8'b1010_0110, //main3
r2 = 8'b1010_0101, w2 = 8'b1010_0100, //main2
r1 = 8'b1010_0011, w1 = 8'b1010_0010, //main1
r0 = 8'b1010_0001, w0 = 8'b1010_0000; //main0
assign sda = (out_flag == 1) ? sda_buf[7] : 1'bz;

initial
begin
addr_byte_h = 0;
addr_byte_l = 0;
ctrl_byte = 0;
out_flag = 0;
sda_buf = 0;
State = 2'b00;
memory_buf = 0;
address = 0;
shift = 0;
for(i=0;i<=8191;i=i+1)
memory[i] = 0;
end
always@(negedge sda)
begin
if(scl == 1)
begin
State = State + 1;
if(State == 2'b11)
disable write_to_eeprom;
end
end

always@(posedge sda)
begin
if(scl == 1) 
stop_W_R;
else
begin
casex(State)
2'b01:begin
read_in;
if(ctrl_byte == w7 || ctrl_byte == w6
|| ctrl_byte == w5 || ctrl_byte == w4
|| ctrl_byte == w3 || ctrl_byte == w2
|| ctrl_byte == w1 || ctrl_byte == w0)
begin
State = 2'b10;
write_to_eeprom; 
end
else
State = 2'b00;
end
2'b11:
read_from_eeprom;
default:
State = 2'b00;
endcase
end
end 
task stop_W_R;
begin
State = 2'b00;
addr_byte_h = 0;
addr_byte_l = 0;
ctrl_byte = 0;
out_flag = 0;
sda_buf = 0;
end
endtask

task read_in;
begin
shift_in(ctrl_byte);
shift_in(addr_byte_h);
shift_in(addr_byte_l);
end
endtask

task write_to_eeprom;
begin
shift_in(memory_buf);
address = {addr_byte_h[4:0], addr_byte_l};
memory[address] = memory_buf;
State = 2'b00;
end
endtask

task read_from_eeprom;
begin
shift_in(ctrl_byte);
if(ctrl_byte == r7 || ctrl_byte == w6
|| ctrl_byte == r5 || ctrl_byte == r4
|| ctrl_byte == r3 || ctrl_byte == r2
|| ctrl_byte == r1 || ctrl_byte == r0)
begin
address = {addr_byte_h[4:0], addr_byte_l};
sda_buf = memory[address];
shift_out;
State = 2'b00;
end
end
endtask
task shift_in;
output[7:0]shift;
begin
@(posedge scl) shift[7] = sda;
@(posedge scl) shift[6] = sda;
@(posedge scl) shift[5] = sda;
@(posedge scl) shift[4] = sda;
@(posedge scl) shift[3] = sda;
@(posedge scl) shift[2] = sda;
@(posedge scl) shift[1] = sda;
@(posedge scl) shift[0] = sda;
@(negedge scl)
begin
#(`timeslice);
out_flag = 1;
sda_buf = 0;
end
@(negedge scl)
begin
#(`timeslice-250);
out_flag = 0;
end
end
endtask
task shift_out;
begin
out_flag = 1;
for(i=6; i>=0; i=i-1)
begin
@(negedge scl);
#`timeslice;
sda_buf = sda_buf << 1;
end
@(negedge scl) #`timeslice sda_buf[7] = 1;
@(negedge scl) #`timeslice out_flag = 0;
end
endtask
endmodule

仿真结果如下，在scl为高电平时sda由高变低，表示传输开始。数据在时钟高电平时保持稳定，在时钟低电平时变化。第一位到第七位为从机地址1010000 ，第八位为0，表示写操作，第九位为从机应答，低低电平表示应答成功。
在这里插入图片描述

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FPGA Verilog IIC控制EEPROM

IIC通信协议简介IIC只有两根线，一根SDA数据线，一根SCL数据线。1、除了开始标志和结束标志，其余时间不允许在时钟信号高电平时数据线信号产生变化。因此写数据需要在时钟低电平时写入，读数据要在时钟高电平时读出。2、开始和结束标志：在时钟线为高电平时，数据线电平由高变低（开始），数据线电平由低变高（结束）。3、主机每发送8位数据，从机都会回应一位低电平的ACK信号。EEPROM读写操作的流程在进行写操作时，先写入从机地址（每个器件的从机地址都是固定的）以及读写标志位，再写入数据地址（有的是8位
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