硬件描述语言

transcode_led

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity transcode_led is
	port
	(
		x	 :in std_logic_vector(3 downto 0);
		y	 :out std_logic_vector(7 downto 0)
		
	);
end entity transcode_led;

architecture rtl of transcode_led is
begin
		PROCESS(x)IS
		BEGIN
			CASE(x)IS--共阳极数码管低电平点亮
									--abcdefg
				WHEN "0000"=>y<="00000011";
				WHEN "0001"=>y<="10011111";
				WHEN "0010"=>y<="00111111";
				WHEN "0011"=>y<="00001101";
				WHEN "0100"=>y<="10011001";
				WHEN "0101"=>y<="01001001";
				WHEN "0110"=>y<="01000001";
				WHEN "0111"=>y<="00011111";
				WHEN "1000"=>y<="00000001";
				WHEN "1001"=>y<="00001001";
				WHEN "1010"=>y<="00010001";
				WHEN "1011"=>y<="11000001";
				WHEN "1100"=>y<="01100011";
				WHEN "1101"=>y<="10000101";
				WHEN "1110"=>y<="01100001";
				WHEN "1111"=>y<="01110001";
			END CASE;
		END PROCESS;
end rtl;

ff_jk

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ff_jk is
	port
	(
		clk,clr,j,k	   :in std_logic;
		q,nq	:buffer std_logic
	);
end entity ff_jk;

architecture rtl of ff_jk is
	
begin
 
	PROCESS(clk)IS
	BEGIN
		IF(clk'EVENT AND clk='1')THEN
			IF(clr='0')THEN
			q<='0';
			nq<='1';
			ELSE 
				IF((j='0')AND(k='1')) THEN--置0
						q<='0';
						nq<='1';
				ELSIF ((j='1')AND(k='0')) THEN--置1
						q<='1';
						nq<='0';
				ELSIF((j='1')AND(k='1'))THEN--反转
					q<=NOT q;
					nq<=NOT q;
				END IF;
				END IF;
		 	END IF;
	   END PROCESS;
end rtl;

ff_d

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ff_d is
	port
	(
		clk,clr,d,set   :in std_logic;
		q,nq	:buffer std_logic
	);
end entity ff_d;

architecture rtl of ff_d is
	
begin
 
	PROCESS(clk,clr,d,set)IS
	BEGIN
		IF(clk'EVENT AND clk='1')THEN
			IF(clr='0')THEN
			q<='0';
			nq<='1';
			ELSE 
				IF(set='0') THEN
						q<='0';
						nq<='1';
				ELSE
					IF(d='0')THEN q<='0';nq<='1';
					ELSIF(d='1')THEN q<='1';nq<='0';
					q<=NOT q;
					nq<=NOT q;
					END IF;
				END IF;
		 	END IF;
			END IF;
	   END PROCESS;
end rtl;

counter10

   library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter10 is
	port
	(
		clk,clr	   :in std_logic;
		q	:buffer std_logic_vector(3 downto 0);
		co	:out std_logic
	);
end entity counter10;

architecture rtl of counter10 is
begin
 
	PROCESS(clk)IS
	BEGIN
		IF(clk'EVENT) AND (clk='1')THEN
			IF(clr='0')THEN
			q<="0000";co<='0';
			ELSE
				IF(q="1001")THEN
				q<="0000";co<='1';
				ELSE 
				q<=q+'1';co<='0';
				END IF;
			END IF;
		END IF;
	END PROCESS;
	
end rtl;

L_shifter8

library ieee;
use ieee.std_logic_1164.all;

entity L_shifter8 is
	port	( clk,clr,si  : in 	std_logic;
		  d	       : buffer    std_logic_vector(7 downto 0);
		  so	       : out         std_logic  );
end entity L_shifter8;
architecture rtl of L_shifter8 is
begin
	process (clk)
	begin	
		if (clk'event) and (clk='1') then
			if clr = '0' then
				d <= "00000000"; so <= '0';
			else
				d(7 downto 1) <= d(6 downto 0); 
				d(0) <= si;
				so <= d(6);
			end if;
		end if;
	end process;
end rtl;

encode_16_4

    library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity encode_16_4 is
	port
	(
		x	   :in std_logic_vector(15 downto 0);
		y     :out std_logic_vector(3 downto 0);
		nul 	:out std_logic;
		inv 	:out std_logic
	);
end entity encode_16_4;

architecture rtl of encode_16_4 is

	
begin
 
	PROCESS(x)IS
	BEGIN
		CASE x IS
			WHEN "1111111111111110"=>y<="0000";nul<='0';inv<='0';
			WHEN "1111111111111101"=>y<="0001";nul<='0';inv<='0';
			WHEN "1111111111111011"=>y<="0010";nul<='0';inv<='0';
			WHEN "1111111111110111"=>y<="0011";nul<='0';inv<='0';
			WHEN "1111111111101111"=>y<="0100";nul<='0';inv<='0';
			WHEN "1111111111011111"=>y<="0101";nul<='0';inv<='0';
			WHEN "1111111110111111"=>y<="0110";nul<='0';inv<='0';
			WHEN "1111111101111111"=>y<="0111";nul<='0';inv<='0';
			WHEN "1111111011111111"=>y<="1000";nul<='0';inv<='0';
			WHEN "1111110111111111"=>y<="1001";nul<='0';inv<='0';
			WHEN "1111101111111111"=>y<="1010";nul<='0';inv<='0';
			WHEN "1111011111111111"=>y<="1011";nul<='0';inv<='0';
			WHEN "1110111111111111"=>y<="1100";nul<='0';inv<='0';
			WHEN "1101111111111111"=>y<="1101";nul<='0';inv<='0';
			WHEN "1011111111111111"=>y<="1110";nul<='0';inv<='0';
			WHEN "0111111111111111"=>y<="1111";nul<='0';inv<='0';
			WHEN "1111111111111111"=>y<="0000";nul<='1';inv<='0';
			WHEN OTHERS=>y<="0000";nul<='1';inv<='1';
		END CASE;
	
	END PROCESS;
	
end rtl;