HLS *out 探索

探索1：

*data 端口 表示 一 wire 类型接口，虽然c层面接口只有一个端口 *data，但是转换对应的verilog接口逻辑是   data_out = data_in,会自动出现输入端口和输出端口、输出端口valid，值得注意的是：valid是一个 伪时序逻辑，数据端口都是 wire。仿真发现 会短暂出现 输出的数据再次进入运算的情况发生，不建议使用。

void	gain_10
	(
			uint32	*data
	)
{
	*data	=	*data * 10	;
}

对应的verilog行为

// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="gain_10,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z100ffg900-2,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.245000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=39,HLS_VERSION=2018_2}" *)

module gain_10 (
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        data_V_i,
        data_V_o,
        data_V_o_ap_vld
);


input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [31:0] data_V_i;
output  [31:0] data_V_o;
output   data_V_o_ap_vld;

reg data_V_o_ap_vld;

wire   [31:0] tmp_fu_29_p2;
wire   [31:0] tmp_1_fu_35_p2;

always @ (*) begin
    if ((ap_start == 1'b1)) begin
        data_V_o_ap_vld = 1'b1;
    end else begin
        data_V_o_ap_vld = 1'b0;
    end
end

assign ap_done = ap_start;

assign ap_idle = 1'b1;

assign ap_ready = ap_start;

assign data_V_o = (tmp_fu_29_p2 + tmp_1_fu_35_p2);

assign tmp_1_fu_35_p2 = data_V_i << 32'd1;

assign tmp_fu_29_p2 = data_V_i << 32'd3;

endmodule //gain_10

探索2：

*dout 和 *din 都是 wire类型接口，*dout的valid 是一块 伪时序逻辑，整块逻辑为组合逻辑

从code发现  ，hls将 data*10   =  data*8 + data*2  ，使用移位实现。 仿真结果正常，端口可以这样操作

void	point
	(
		uint32	*dout	,
		uint32	*din
	)
{

	*dout = *din*10	;
}

 对应的verilog code  ，

// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="point,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z100ffg900-2,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.245000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=39,HLS_VERSION=2018_2}" *)

module point (
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        dout_V,
        dout_V_ap_vld,
        din_V
);


input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
output  [31:0] dout_V;
output   dout_V_ap_vld;
input  [31:0] din_V;

reg dout_V_ap_vld;

wire   [31:0] tmp_fu_31_p2;
wire   [31:0] tmp_1_fu_37_p2;

always @ (*) begin
    if ((ap_start == 1'b1)) begin
        dout_V_ap_vld = 1'b1;
    end else begin
        dout_V_ap_vld = 1'b0;
    end
end

assign ap_done = ap_start;

assign ap_idle = 1'b1;

assign ap_ready = ap_start;

assign dout_V = (tmp_fu_31_p2 + tmp_1_fu_37_p2);

assign tmp_1_fu_37_p2 = din_V << 32'd1;

assign tmp_fu_31_p2 = din_V << 32'd3;

endmodule //point

探索3：

*dout 和 din 都是 wire类型接口，*dout的valid 是一块 伪时序逻辑，整块逻辑为组合逻辑

从code发现  ，hls将 data*10   =  data*8 + data*2  ，使用移位实现。 仿真结果正常，端口可以这样操作

void	point_1
	(
		uint32	*dout	,
		uint32	din
	)
{

	*dout = din*10	;
}

对应verilog

// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="point_1,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z100ffg900-2,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.245000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=39,HLS_VERSION=2018_2}" *)

module point_1 (
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        dout_V,
        dout_V_ap_vld,
        din_V
);


input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
output  [31:0] dout_V;
output   dout_V_ap_vld;
input  [31:0] din_V;

reg dout_V_ap_vld;

wire   [31:0] tmp_fu_31_p2;
wire   [31:0] tmp_1_fu_37_p2;

always @ (*) begin
    if ((ap_start == 1'b1)) begin
        dout_V_ap_vld = 1'b1;
    end else begin
        dout_V_ap_vld = 1'b0;
    end
end

assign ap_done = ap_start;

assign ap_idle = 1'b1;

assign ap_ready = ap_start;

assign dout_V = (tmp_fu_31_p2 + tmp_1_fu_37_p2);

assign tmp_1_fu_37_p2 = din_V << 32'd1;

assign tmp_fu_31_p2 = din_V << 32'd3;

endmodule //point_1

对比发现   *dout = *din  和  *dout  = din  是等效的，生成的verilog和rtl仿真结构都一致。