systemverilog常用code——counter案例

kanasu

已于 2024-01-06 14:53:24 修改

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分类专栏： systemverilog 文章标签：开发语言

于 2023-12-01 14:16:26 首次发布

本文链接：https://blog.csdn.net/m0_46795246/article/details/134713515

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项目场景一

需要在sequence里写一个counter来记录发包的数量

代码展示

  fork
    //第一个begin end语句块用来发包  
    begin
      for (int idx=0;idx<130;idx++)begin
        `uvm_info(get_type_name(),$sformatf("idx is %0d", idx), UVM_HIGH)        
        std::randomize(rd) with { rd inside {1'b0,1'b1}; };
        if(rd==1)begin
          mrd(rd_cfg);//发出read包
        end else begin
          mwr(wr_cfg);//发出write包
        end
      end
    end
    //第二个begin end语句块用来记录发包的数量
    begin
      fork:cnt_block
        forever begin
          @(p_sequencer.if_i.arid)begin
            `uvm_info("cnt ongoing", $sformatf("realtime is %t", $realtime), UVM_HIGH);
            #10ps;//延迟一小段时间是因为arid和arvalid可能同时跳变
            if (p_sequencer.if_i.arvalid)begin
              arvalid_cnt++;
              `uvm_info("cnt ongoing", $sformatf("realtime is %t", $realtime), UVM_HIGH);
            end
          end
        end
        forever begin
          @(p_sequencer.if_i.awid)begin
            `uvm_info("cnt ongoing", $sformatf("realtime is %t", $realtime), UVM_HIGH);
            #10ps;
            if (p_sequencer.if_i.awvalid)begin
              awvalid_cnt++;
              `uvm_info("cnt ongoing", $sformatf("realtime is %t", $realtime), UVM_HIGH);
            end
          end
        end
        begin
          user_event.wait_trigger;//该event trigger即结束cnt_block
        end
      join_any
      disable cnt_block;
      cnt_sum = arvalid_cnt+awvalid_cnt;
      `uvm_info("cnt end", $sformatf("cnt_sum, arvalid_cnt, awvalid_cnt = %0d, %0d, %0d",cnt_sum, arvalid_cnt, awvalid_cnt), UVM_LOW);
    end
  join

项目场景二

需要在sequence里写一个counter来记录时间，超时并报timeout

代码展示

        fork 
            begin
                for (int i =0; i<10; i++) begin
				    @(posedge env.if_i.clk);
                    $display ("%s @ %0t: time_start", clk_name, $realtime); //unit is ns
                    time_start = $realtime;
                    @posedge env.if_i.clk);
                    $display ("%s @ %0t: time_end", clk_name, $realtime);
                    time_end = $realtime;
                    period[i] = time_end-time_start;
                    sum += period[i];
                end
                freq = 10/sum; 
                sum = 0;
            end

            begin            
				#500000ns
                sum = 0;
                `uvm_error(get_type_name(), $sformatf("%s clock monitor TIMEOUT!", clk_name)); 
            end
        join_any
        disable fork;