systemverilog常用约束案例

项目场景一

如何约束AXI发包不跨4KB边界？

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代码展示

addr[11:0]+burst_size*burst_len < 'd4096;

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项目场景二

如何约束PCIe发TLP包不跨4KB边界？

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注意：PCIe TLP包的length field指的是Dword的length

代码展示

addr[11:2]+length < 'd1024;

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项目场景三

如何约束PCIe发TLP包不跨512B边界？

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注意：PCIe TLP包的length field指的是Dword的length

代码展示

addr[8:2]+length < 'd128;

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项目场景四

如何约束PCIe ATS successful translation completion中的Translated Address[63:12]符合协议规定的格式？

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代码展示

    /** Size of translation field in payload, including the S field(translation_size[0]).它其实就是translated address[63:12]*/
    rand bit[52:0] translation_size;
    /** Indicates number of bits set in translation_size. 即translation_size里有几个1*/
    rand int num_bits_set_in_translation_size;

    
    foreach(payload[i]) {
      //Constraints added for translation_size and other translation fields.
      if(i%2 != 0) {
        payload[i][10] == non_snooped_access[i];
        payload[i][2:0] == {untranslated_access_only[i], write_access[i], read_access[i]};
        (payload[i][31:11] & translation_size[20:0]) == translation_size[20:0];//约束translation_size为1的地方，payload必须是1
        (payload[i] & (32'hffff_ffff ^ (32'h0000_0001 << (11 + num_bits_set_in_translation_size)))) == payload[i];//约束translation_size的最低位的0（从右往左数，第一个0的地方），payload在该位置也必须是0
      } else {
        (payload[i] & translation_size[52:21]) == translation_size[52:21];//同上
        if(num_bits_set_in_translation_size > 20) {
          (payload[i] & (32'hffff_ffff ^ (32'h0000_0001 << (11 + num_bits_set_in_translation_size - 32)))) == payload[i];//同上
        }
      }
    }

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