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RSS订阅原创 PCIe进阶之TL：Request Handling Rules
PCIe；Handling of Received TLPs；Request Handling Rules
2024-09-16 21:45:48
1032
1
原创 PCIe进阶之TL：Completion Rules & TLP Prefix Rules
PCIe；Completion Rules；TLP Prefix Rules；Local TLP Prefix Processing；End-End TLP Prefix Processing
2024-09-16 14:04:01
1258
原创 PCIe进阶之TL：Memory, I/O, and Configuration Request Rules & TPH Rules
PCIe；Memory, I/O, and Configuration Request Rules；TPH Rules
2024-09-15 22:20:22
1762
1
原创 PCIe进阶之TL：First/Last DW Byte Enables Rules & Traffic Class Field
PCIe；First/Last DW Byte Enables Rules；Transaction Descriptor；Traffic Class Field
2024-09-15 18:21:39
1486
原创 PCIe进阶之TL：TLP Digest Rules & Routing and Addressing Rules
PCIe；TLP Digest Rules；Address-Based Routing Rules；ID Based Routing Rules
2024-09-15 16:56:45
1204
原创 PCIe进阶之TL：Common Packet Header Fields & TLPs with Data Payloads Rules
PCIe；Transaction Layer Protocol；Common Packet Header Fields；TLPs with Data Payloads Rules
2024-09-15 13:53:32
1561
原创 PCIe进阶之TL：Address Spaces, Transaction Types, and Usage
PCIe；Transaction Layer；Address Spaces；Transaction Types
2024-09-15 12:59:22
755
原创 PCIe进阶之Gen3 Physical Layer Receive Logic（一）
PCIe Gen3 Physical Layer Receive Logic；Differential Receiver；CDR（Clock and Data Recovery）；Receiver Clock Compensation Logic
2024-01-12 19:44:00
1291
原创 PCIe进阶之Gen3 Physical Layer Transmit Logic（二）
PCIe Gen3 Physical Layer Transmit Logic；Byte Striping；Scrambling；Serializer
2024-01-11 20:21:10
1012
原创 PCIe进阶之Gen3 Physical Layer Transmit Logic（一）
Gen3 Physical Layer Tx Logic；Multiplexer；Byte Striping
2024-01-09 20:25:39
620
原创 PCIe进阶之Encoding for 8.0 GT/s
Gen3 Encoding；Block Alignment；Ordered Set Block；Data Stream；Data Block
2024-01-09 20:15:32
1338
原创 PCIe进阶之Gen3 Physical Layer-Logic Introduction
PCIe；Gen3 Physic Layer Introduction；128b/130b encode；Equalization
2024-01-08 16:46:27
926
原创 PCIe之LTSSM-Recovery.Equlization
PCIe；LTSSM；Recovery；Recovery.Equlization
2023-11-06 15:18:33
1475
原创 PCIe之Transmitter Coefficients Rules
PCIe；Transmitter Coefficients；Encoding of Preset
2023-10-19 15:03:08
970
原创 PIPE Interface解析之Clock Tolerance Compensation & Error Detection & Polarity Inversion
PIPE Interface；Clock Tolerance Compensation；Error Detection；Polarity Inversion
2023-10-10 20:51:03
555
原创 PIPE Interface解析之信号解析（SerDes&Original共有）
PIPE Interface；SerDes；Original；Data Interface；Command Interface；Status Interface；
2023-10-04 15:32:24
1377
2
原创 PCIe Retimer之Execution Mode Slave Loopback
PCIe Retimer；Execution Mode；Slave Loopback；
2023-09-28 09:48:19
522
原创 PCIe Retimer之Execution Mode Link Equalization
PCIe Retimer；Execution Mode；Link Equalization；
2023-09-27 09:25:38
669
原创 PCIe Retimer之Execution Mode Compliance Load Board
PCIe Retimer；Execution Mode；Compliance Load Board；
2023-09-26 09:25:57
570
1
原创 PIPE Interface解析之Tx Margining & De-emphasis & Rx Detection & Beacon
PIPE Interface；Tx Margining；De-emphasis；Rx Detection；Beacon；
2023-09-25 09:48:45
954
1
原创 PIPE Interface解析之SerDes/Original架构（专有）信号解析
PIPE Interface；SerDes架构信号解析；Original架构信号解析；
2023-09-24 10:32:50
1025
1
原创 PIPE Interface解析之PIPE SerDes/Original架构
PIPI Interface；SerDes架构；Original架构；PHY Tx结构；PHY Rx结构；
2023-09-23 13:11:29
1851
1
原创 SystemVerilog语言之约束的技巧和技术
SystemVerilog；约束的技巧和技术；随机函数；dist；inside；randomize()with；rand_mode；constraint_mode;
2023-09-03 10:37:11
1057
PCIe Gen1~Gen5的PIPE Interface学习文档
2023-10-05
High-Speed-Links-Circuits-and-Systems
2023-09-24
数字IC验证-SystemVerilog语言
2023-09-17
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