一个 1/2分频器的可综合模型。
模块设计方法:
module half(res_n, clk_in, clk_out);
input res_n, clk_in;
output clk_out;
reg clk_out;
always@(posedge clk_in)begin
if (!res_n)
clk_out = 0;
else
clk_out = ~clk_out;
end
endmodule
测试模块方法:
`timescale 1ns/1ns
`define clk_cycle 50
module half_tb();
reg rst_n, clk_in;
wire clk_out;
always #clk_cycle clk_in = ~clk_in; // 产生测试时钟
initial begin
clk_in = 0; rst_n = 1;
#10 rst_n = 0;
#110 rst_n = 1;
#100000 $stop;
end
half half_t0(
.rst_n(rst_n),
.clk_in(clk_in),
.clk_out(clk_out)
);
endmodule
Schematic