一个可综合风格的分频器,可将10MHz的时钟分频为500kHz的时钟。
模块设计方法:
module division(reset, f10m,f500k);
input f10m, reset;
output f500k;
reg f500k;
reg[7:0] j;
always@(posedge f10m)
if(!reset)begin // 低电平复位
f500k <= 0;
j <= 0;
end
else begin
if(j == 19)begin // 对计数器进行判断,以确定f500k信号是否反转
j <= 0;
f500k <= ~f500k;
end
else
j <= j + 1;
end
endmodule
测试模块方法:
`timescale 1ns/100ps
`define clk_cycle 50
module division_tb();
reg F10M, Reset;
wire F500k_clk;
always #clk_cycle F10M = ~F10M;
initial begin
Reset = 1; F10M = 0;
#100 Reset = 0;
#100 Reset = 1;
#100000 $stop;
end
division division_t0(
.reset(Reset),
.f10m(F10M),
.f500k(F500k_clk)
);
endmodule
Schematic