一.开发板RGB灯的硬件原理图如下:
RGB灯低电平有效。
及其所对应的FPGA的管脚:
二.verilog代码实现
1.定义三色灯对应状态
parameter Red = 3'b110;
parameter Green = 3'b101;
parameter Blue = 3'b011;
2.每隔一秒进行RGB灯的状态的切换(其中CNT=24000000)
always @(posedge clk_24M or negedge rst)
begin
if (!rst)
begin
cnt_time <= 0;
state <= Red;
end
else if(cnt_time == CNT - 1'b1)
begin
cnt_time <= 0;
state <= state + 1'b1;
end
else
cnt_time <= cnt_time + 1'b1;
end
3.赋值输出:
always@(*)
begin
case(state)
3'd0:led_rgb <= Red;
3'd1:led_rgb <= Green;
3'd2:led_rgb <= Blue;
3'd3:led_rgb <= Red;
3'd4:led_rgb <= Green;
3'd5:led_rgb <= Blue;
3'd6:led_rgb <= Green;
3'd7:led_rgb <= Red;
default:state <= state;
endcase
end
assign led_r = led_rgb[0];
assign led_g = led_rgb[1];
assign led_b = led_rgb[2];