计算机组成原理 设计一个8位的数据寄存器DR

dr寄存器如图所示 

 

testbench及 相应模块如下

module dr(clk,rst,drload,din,dout);
input clk,rst,drload;
input [7:0] din;
output reg[7:0] dout;
always@(posedge clk or negedge rst)
begin
	if(rst==0)
		dout <= 0;
	else if(drload)
		dout <= din;
end
endmodule


`timescale 10ns/1ns
module dr_tb();
reg clk;
reg [7:0] data_in;
reg rst;
reg drload;
wire[7:0]data_out;
dr mreg(.clk(clk),.rst(rst),.drload(drload),.din(data_in),.dout(data_out));
initial
begin
	clk=0;	rst=1;	drload=0;	data_in=8'd23;
end
always	#50	clk = ~clk;	
initial
begin
#10	rst = 0;
#15	drload = 1;
#10	rst = 1;
#20	drload = 0;
#30	drload = 1;
#15	data_in=8'd12;	
#25	drload = 0;
#25 	rst = 0;data_in=8'd47;
#50	$finish;
end
endmodule