计算机组成与CPU设计实验——算术逻辑单元

 前提知识

• 带符号数的表示

 

 

• 移位运算

 

 

 实验要求

将操作数看作带符号数的补码进行比较。

 

 实验代码

`default_nettype none 
module VirtualBoard (
    input  logic  CLOCK,      // 10 MHz Input Clock 
    input  logic [19:0] PB,   // 20 Push Buttons, logical 1 when pressed
    input  logic [35:0] S,    // 36 Switches
    output logic [35:0] L,    // 36 LEDs, drive logical 1 to light up
    output logic  [7:0] SD7,  // 8 common anode Seven-segment Display
    output logic  [7:0] SD6,
    output logic  [7:0] SD5,
    output logic  [7:0] SD4,
    output logic  [7:0] SD3,
    output logic  [7:0] SD2,
    output logic  [7:0] SD1,
    output logic  [7:0] SD0
); 

/** The input port is replaced with an internal signal **/
wire signed [3:0] X = S[7:4];
wire signed [3:0] Y = S[3:0];
wire [3:0] ALU = S[12:9];

/************* The logic of this experiment *************/
localparam N = 4;
wire [N-1:0] F; 
logic [N:0] result; // Bit width is N+1 bits
logic bigequ,sml,notequ,equ;

always_comb 
begin
   case(ALU)
      4'sb0001: result = X + Y;        
      4'sb0010: result = X - Y;
      4'b0011: result = {1'b0, (X & Y)};
      4'b0100: result = {1'b0, (X | Y)};
	  4'b0101: result = {1'b0, (X ^ Y)};
      4'b0110: result = {1'b0, (X >>> Y[1:0])};
      4'b0111: result = {1'b0, (X << Y[1:0])};
      4'b1000: result = {1'b0, (X >> Y[1:0])};
      default: result = {4{1'bx}};
   endcase
end

assign F = result[N-1:0];
assign bigequ = (X>=Y);
assign sml = (X<Y);
assign notequ = (X!=Y);
assign equ = (X==Y);

/****** Internal signal assignment to output port *******/
assign L[12:9] = F;
assign L[21:18] = {bigequ,sml,notequ,equ};

endmodule