RISC-V 实现整数运算指令（Part 2）

 验证R型运算指令

源代码

package alu_defs;

   enum logic [3:0] {
      ADD = 4'b0001,
      SUB = 4'b0010,
      AND = 4'b0011,
      OR  = 4'b0100,
      XOR = 4'b0101,
      SRA = 4'b0110,
      SLL = 4'b0111,
      SRL = 4'b1000
   } aluop;

endpackage


`default_nettype none
// --------------------------------------------------------------------
// CPU 模块
// --------------------------------------------------------------------
module CPU
 #(
     parameter DATAWIDTH = 32,
     parameter ADDRWIDTH = 32
 )
(
    input  wire iCPU_Reset,
    input  wire iCPU_Clk,
    // 指令存储器接口
    output wire [ADDRWIDTH-1:0] oIM_Addr,   //指令存储器地址
    input  wire [DATAWIDTH-1:0] iIM_Data,   //指令存储器数据
    // 数据存储器接口
    input  wire [DATAWIDTH-1:0] iReadData,  //数据存储器读数据
    output wire [DATAWIDTH-1:0] oWriteData, //数据存储器写数据
    output wire [ADDRWIDTH-1:0] oAB,        //数据存储器地址
    output wire oWR,                        //数据存储器写使能
    // 连接调试器的信号
    output wire [ADDRWIDTH-1:0] oCurrent_PC,
    output wire oFetch,
    input  wire iScanClk,
    input  wire iScanIn,
    output wire oScanOut,
    input  wire [1:0] iScanCtrl
);

   /** The input port is replaced with an internal signal **/
   wire   clk   = iCPU_Clk;
   wire   reset = iCPU_Reset;

   // Instruction parts
   //PC
   logic [31:0] pc, nextPC;
   logic [31:0] instruction; // instruction code
   assign nextPC = pc + 4;   /*-TODO 目前仅支持PC+4，增加分支指令时需修改 -*/

   // DataReg
   DataReg #(32) pcreg(.iD(nextPC), .oQ(pc), .Clk(clk), .Reset(reset), .Load(1'b1));
   assign oIM_Addr = pc;         // 连接指令存储器的地址端口
   assign instruction = iIM_Data;// 连接指令存储器的数据端口

   // Instruction decode
   logic [6:0] opcode;
   logic [2:0] funct3;
   logic [6:0] funct7;
   logic [4:0] ra1,ra2,wa;
   assign funct7 = instruction[31:25];
   assign ra2    = instruction[24:20];
   assign ra1    = instruction[19:15];
   assign funct3 = instruction[14:12];
   assign wa     = instruction[11:7];
   assign opcode = instruction[6:0];

   // Control unit
   logic cRegWrite;
   logic [3:0] aluOp;
   logic [4:0] cImm_type;  //{J,U,B,S,I}
   logic immToAlu;
   Controller controller(
      .iOpcode(opcode),
      .iFunct3(funct3),
      .iFunct7(funct7),
      /*-TODO 随着指令的增加，相应添加端口信号 -*/
      .oRegWrite(cRegWrite),
      .oImm_type(cImm_type),
      .oALUop(aluOp),
      .oImmToAlu(immToAlu)
   );

   // Immediate data gener