S32K144 ADC硬件触发源

最新推荐文章于 2024-02-23 18:34:17 发布

IT LIGEN

最新推荐文章于 2024-02-23 18:34:17 发布

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4.3 配置的延迟小于ADC转换时间且大于4个总线时钟周期

4.4 配置的延时大于ADC转换时间

1、ADC触发源

（1） ADC一般支持两种硬件触发源：

一种是使用PDB触发ADC（默认）。
另一种是使用TRGMUX触发ADC。
SIM_ADCOPT[ADCxTRGSEL]字段用于选择ADC触发源。

（2）PDB为ADC生成触发器和预触发器（ADC和PDB成对操作，如PDB0;ADC0和PDB1;ADC1)，每个PDB通道有多达8个预触发器用于ADC通道控制。

（3）每个ADC最少一个外部引脚（用于支持TRGMUX）

软件必须确定相对优先级
在单个正在进行的转换完成后开始新的转换

（4） CMP out、LPIT、RTC和LPTMR能够通过TRGMUX触发每个ADC。（详细信息请参阅TRGMUX章节的TRGMUX模块互连)

（5）LPIT支持多达4个预触发器，限制在每个ADC的ADHWTS0-ADHWTS3上使用。对于其余的外设，需要进行软件配置以提供预触发器（参见SIM_ADCOPT[ADCxSWPRETRG]配置软件预触发）。

注：对于TRGMUX触发，最多只支持4个预触发器。每个PDB支持4个触发通道，每个通道支持8个预触发器。

（6）ADC0-PDB0 ADC触发源实例框图如下：

注：当使用TRGMUX时，只有LPIT支持预触发器。对于其他外设，需要使用SIM_ADCOPT[ADCxSWPRETRG]配置软件预触发器。

1.1 PDB触发方案

PDB触发方案是ADC的默认和建议触发方法。

一个ADC和一个PDB作为一对工作:PDB0-ADC0, PDB1-ADC1。PDB0和PDB1的触发源可以分别通过TRGMUX_PDB0和TRGMUX_PDB1配置。这里以PDB0-ADC0为例说明PDB触发方案：

设置SIM_ADCOPT[ADCxTRGSEL]=0。选择PDB0通道0作为ADC触发源。
PDB0预触发器将直接连接到ADC0 ADHWTS端口来控制通道。
ADC0 COCO信号直接反馈到PDB0去激活PDB锁状态。

下图是使用PDB触发ADC的典型案例：

1.2 TRGMUX触发方案

TRGMUX支持许多触发器源（CMP out、LPIT、RTC和LPTMR）。这里以LPIT为例说明TRGMUX触发方案：（LPIT最多支持4个通道（ADHWTSA-ADHWTSD），每个通道都有一个触发器和一个预触发器。）

设置SIM_ADCOPT[ADCxTRGSEL]=1。选择TRGMUX out作为ADC触发源。
配置TRGMUX选择LPIT触发器作为ADC触发器和预触发源。
TRGMUX仅支持每个ADC最多4个预触发器（pre-trigger0 ~ pre-trigger3；其它预触发器不能与TRGMUX一起使用）。
在这个例子中不需要ADC COCO。但软件必须适应每个ADC转换之间的间隔时间。
使用TRGMUX允许使用单个LPIT同时触发两个ADC。这是使用TRGMUX触发而不使用PDB触发的好处之一。

注：对于PDB和LPIT以外的触发源，需要软件提供ADC预触发。

2、硬件触发和通道选择

ADC模块有一个可选择的异步硬件转换触发器ADHWT，当SC2[ADTRG]被设置，并且发生了一个硬件触发选择事件ADHWTSn时，ADHWT被启用。

当ADHWT源（PDB/TRGMUX）启用且硬件触发使能（SC2[ADTRG] = 1）时，发生硬件触发选择事件ADHWTSn后，ADHWT上升沿发起转换。如果在发现触发器上升沿时正在进行转换，则忽略上升沿。

在连续转换模式中，只有初始的上升沿可以启动连续转换，ADC继续在启动转换的同一个SC1n寄存器上进行转换，直到转换终止。

硬件触发选择事件ADHWTSn，必须在ADHWT信号接收之前设置。如果不满足这些条件，转换器可能会忽略触发器或使用不正确的配置。如果在转换期间断言了硬件触发选择事件，则它必须保持断言状态，直到当前转换结束，并保持设置，直到接收到触发新转换的ADHWT信号。选择用于转换的通道和状态字段取决于主动触发选择信号：

ADHWTSA active selects SC1A.
ADHWTSn active selects SC1n.

当转换完成时，结果被放在与接收到的ADHWTSn相关联的Rn寄存器中。例如:

ADHWTSA active selects RA register.
ADHWTSn active selects Rn register.

然后设置与收到的ADHWTSn相关联的转换完成标志，即SC1n[COCO]，如果相应的转换完成中断已使能，则产生中断，即SC1[AIEN]=1。

注意：在转换完成之前选择多个ADHWTSn将导致不可预测的结果。为了避免这种情况，在转换完成之前只选择一个ADHWTSn。

3、触发器选择

Any combination of trigger enable and trigger can be selected; they are independent of each other. But after it has been selected, it cannot be changed on-the-fly. There are defined steps to change the trigger and enable sources (trigger and pre-trigger source).

改变触发源可以使用以下两种方式的任意一种即可：

方式一：

Stop the current trigger generation unit.
Wait for a time period equals to total of 2.5 cycle of ADC operating clock and 1.5 cycles of ADC host interface clock, to give time to latch the last trigger, if any.
Poll the status of ADC_SC2[TRGSTLAT] for all 0, it will come to 0 after completing all conversions enqued till that time.
Change the selections for desired source and then
Start the new trigger generation units.

方式二：（该方式可以立即切换源）

Stop the current trigger generation unit
Flush all the queued triggers of trigger handler block by setting ADC_CFG1[CLRLTRG], this will flush all queued triggers except the one under process by ADC, if any
Wait for a time period equals to total of 2.5 cycle of ADC operating clock.
Wait for the status of ADC_SC2[TRGSTLAT] to become all 0.
Change the selections for desired source and then
Start the new trigger generation units.

3、触发器锁定和仲裁

四个较低的触发器（PDB/TRGMUX pre-trigger[3:0]）具有锁存的功能。无论选择哪个触发源，来自该触发源的触发器请求都将被锁定并处理。锁存触发器请求一次一个地呈现给ADC。只有当ADC完成当前触发请求的处理后，才会给出下一个请求。因此，在任何给定时间只处理一个请求，所有其他请求都被锁住。如果一个触发器请求再次出现在任何PDB/TRGMUX pre-trigger[3:0]触发器上，而它正在被ADC处理或已经锁存在触发器处理程序中，则忽略新请求，并在寄存器ADC_SC2[TRGSTERR]中指出该触发器的错误。

The relationship among the trigger requests from the selected source can randomly be (a) one-hot, or (b) simultaneous. 但是，它们将以循环的方式提供服务。例如，在处理了第P个请求后[0 < P <(N-1)]，搜索将从(P+1)开始，接着是(P+2)，直到找到下一个锁存请求。然后，在第(N-1)次触发后，搜索滚动到0，并继续搜索，直到到达P。

要使用多路复用触发器与ADC一起工作，您需要遵循以下不同情况的编程顺序:

Case 1: Initialization/start of conversion:	a. Initialize/reprogram (in case of intermediate start) the SAR ADC for desired operation (see the ADC section for details).
	b. Select the trigger source for the trigger handler block (configuration for this resides in a separate module on the chip; refer to the SIM_ADCOPT register in the SIM chapter).
	c. Configure and start the trigger generation module (PDB or TRGMUX).
Case 2: Changing the trigger source/multiplexer control:	a. Stop the trigger generation module (PDB or TRGMUX).
	b. Do one of the following options: Option 1: 1. Wait for a duration equals to total of 2.5 cycle of ADC operating clock and 1.5 cycles of ADC host interface clock, to give time to latch the last trigger, if any 2. Wait for the latched triggers to be processed and trigger handler to be idle (poll the status of ADC_SC2[TRGSTLAT] for all 0). Option 2: 1. Flush the latched trigger requests in trigger handler block(Write a 1b to the ADC_CFG1[CLRLTRG]). 2. Wait for a time period equals to total of 2.5 cycle of ADC operating clock 3. Wait for the idle status of trigger handler (poll the status of ADC_SC2[TRGSTLAT] for all 0).
	c. Reselect the trigger source for the trigger handler block (configuration for this resides in a separate module on the chip; see the chip-specific section).
	d. Configure and start the trigger generation module (PDB or TRGMUX).
Case 3: Stopping of conversion	a. Stop the trigger generation module (PDB or TRGMUX).
	b. Wait for a duration equals to total of 2.5 cycle of ADC operating clock plus 1.5 cycles of ADC host interface clock, to give time to latch the last trigger, if any.
	c. Wait for the latched triggers to be processed and the trigger handler to be idle (poll the status of ADC_SC2[TRGSTLAT] for all 0s).
	d. Stop the SAR ADC and clear interrupts after required processing (see the ADC section for details).
Case 4: Changing trigger source/multiplexer control in case of ongoing continuous conversion	a. Stop the trigger generation module (PDB or TRGMUX).
	b. Read any configuration register of the ADC.
	c. Write the read value from above in the same register.
	d. This write will abort the ongoing continuous conversion.
	e. Reselect the trigger source for the trigger handler block (configuration for this resides in a separate module on the chip; refer to the SIM_ADCOPT register in the SIM chapter).
	f. Configure and start the trigger generation module (PDB or TRIGMUX).
f. Configure and start the trigger generation module (PDB or TRIGMUX).	a. Read the error status (ADC_SC2[TRGSTERR]).
	b. If any above register bit is 1, then stop the trigger generation module (TRGMUX).
	c. Wait for a duration equals to total of 2.5 cycle of ADC operating clock plus 1.5 cycles of ADC host interface clock, to give time to latch the last trigger, if any.
	d. Wait for the idle status of the trigger handler (poll the status of ADC_SC2[TRGSTLAT] for all 0s).
	e. Clear the above register bit by writing 1 to it.
	f. Wait for the latched triggers to be processed and the trigger handler to be idle (poll the status of ADC_SC2[TRGSTLAT] for all 0s).

4、ADC触发配置

ADC支持两种触发方案（PDB/TRGMUX），通过以下两种途径触发（详情请参见第一节中ADC0-PDB0 ADC触发源实例框图）：

Direct Triggering path through PDB on channel number 4 onward.
Multiplexed triggering path through PDB/TRGMUX on channels 0 to 3 through trigger latching gasket.

除此之外，使用时应该在通道4及以上（ADHWTSE ~ ADHWTSP）使用直接触发路径，在通道0到3（ADHWTSA ~ ADHWTSD）上使用PDB触发，或者在通道0到3上仅使用TRGMUX路径。当使用PDB直接触发方案时，预触发器之间至少间隔4个总线时钟周期。ADC触发配置和行为如下表所示：

(If ADC conversion time < 4 bus clk cycles, configuration 3 in the table above will not be applicable)

注：只有当对应的两个预触发器属于同一个PDB通道时，PDB才提供序列错误。当使用不同的PDB通道时，软件应确保两个预触发器之间的延迟间隔至少为4个总线时钟周期，否则两次转换的转换结果都无效。

对于上表中不同的配置，pre-triggers、trigger、COCO、sequence error、result status信息如下几节所示：

4.1 零延迟配置

Trigger is not raised. The sequence error is reported on both the channels. The ADC result register consists of junk information.

4.2 配置的延迟小于4个总线时钟周期

a. Direct Triggering on channel number 4 onwards through same PDB channel:

Sequence error for second conversion, COCO might be received or might not. Both the conversion results are invalid.

b. Direct Triggering on channel number 4 onwards through different PDB channels:

Sequence error for second conversion is not reported, COCO might be received or might not. Both the conversion results are invalid.

c. Triggering on channels 0-3 through trigger latching gasket:

Sequence error for second conversion is reported, COCO will be received for both channels. Both the conversion results are valid. This is due to the virtue of trigger latching gasket, which latches the trigger requests.

4.3 配置的延迟小于ADC转换时间且大于4个总线时钟周期

a. Direct Triggering on channel number 4 onwards through same PDB channel:

Sequence error for second conversion, COCO will not be received. First conversion results are valid and second conversion results are invalid.

b. Direct Triggering on channel number 4 onwards through different PDB channel：

No sequence error for second conversion, COCO will not be received. First conversion results are valid and second conversion results are invalid.

c. Triggering on channels 0-3 through trigger latching gasket：

4.4 配置的延时大于ADC转换时间

No sequence error, Both COCOs received. Both conversions are valid.

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S32K144 ADC硬件触发源

如果一个触发器请求再次出现在任何PDB/TRGMUX pre-trigger[3:0]触发器上，而它正在被ADC处理或已经锁存在触发器处理程序中，则忽略新请求，并在寄存器ADC_SC2[TRGSTERR]中指出该触发器的错误。除此之外，使用时应该在通道4及以上（ADHWTSE ~ ADHWTSP）使用直接触发路径，在通道0到3（ADHWTSA ~ ADHWTSD）上使用PDB触发，或者在通道0到3上仅使用TRGMUX路径。（2）PDB为ADC生成触发器和预触发器（ADC和PDB成对操作，如PDB0;
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