期末数电实验博客

1.实验目的：
下载Quartur ii软件和modlsim并进行联合仿真。

2.实验内容：
参照哔哩哔哩中教程的代码，然后用quartus ii和modlsim进行联合仿真

3.实验原理：按照视频上的内容，书写和运行代码，完成联合仿真操作。
在这里插入图片描述：
数字逻辑电路P225图6.7：

数字系统设计及仿真，第十一章实验五：

高级数字设计P183例题6.27：

4实验工具：
pc机和Quartur ii软件和modlsim软件。

5.实验截图：
在这里插入图片描述
数字逻辑电路P225图6.7：

数字系统设计及仿真，第十一章实验五：

高级数字设计P183例题6.27：

6.实验视频：

请下载哔哩哔哩动画打开此网址：

【第一个实验，数字逻辑p225，图6.7-哔哩哔哩】https://b23.tv/7kvP2g

【数字系统设计及仿真，第十一章实验五-哔哩哔哩】https://b23.tv/HWom4N

【高级数字设计p183例题6.27-哔哩哔哩】
https://b23.tv/cXnl9j

7.实验代码：
数字逻辑电路P225图6.7：
module trin(Y,E,F);
parameter n=8;
input [n-1:0]Y;
input E;output wire [n-1:0]F;
assign F=E?Y:'bz;
endmodule

数字系统设计及仿真，第十一章实验五：
module mul_pp(mul_a, mul_b, clock, reset_n, mul_out);

input [3:0] mul_a, mul_b;

input clock;

input reset_n;

output [7:0] mul_out;

reg [7:0] mul_out;

reg [7:0] temp_and0;
reg [7:0] temp_and1;
reg [7:0] temp_and2;
reg [7:0] temp_and3;
reg [7:0] temp_add1;
reg [7:0] temp_add2;

always @(posedge clock or negedge reset_n)
begin

if(!reset_n)

begin
mul_out <= 0;
temp_and0 <= 0;
temp_and1 <= 0;
temp_and2 <= 0;
temp_and3 <= 0;
temp_add1 <= 0;
temp_add2 <= 0;
end
else
begin
temp_and0 <= mul_b[0]? {4’b0, mul_a} : 8’b0;
temp_and1 <= mul_b[1]? {3’b0, mul_a, 1’b0} : 8’b0;
temp_and2 <= mul_b[2]? {2’b0, mul_a, 2’b0} : 8’b0;
temp_and3 <= mul_b[3]? {1’b0, mul_a, 3’b0} : 8’b0;
temp_add1 <= temp_and0 + temp_and1;
temp_add2 <= temp_and2 + temp_and3;
mul_out <= temp_add1 + temp_add2;
end
end
endmodule

module tbs52;
reg [3:0] mul_a,mul_b;
reg reset_n,clock;
wire [7:0] mul_out;
integer seed1=9,seed2=12;
always
begin
mul_a=r a n d o m ( s e e d 1 ) ; m u l b = random(seed1); mul_b=random(seed1);mul
b
​
=random(seed2);
#30;
end
initial
begin
reset_n=1;clock=0;
#20 reset_n=0;
#10 reset_n=1;
end
always #15 clock=~clock;
mul_pp mymul (mul_a,mul_b,clock,reset_n,mul_out);
endmodule

module tbs51;

reg [7:0] add1,add2;

reg clock;

reg add_cin;

wire [7:0] add_sum;

wire add_cout;

integer seed1=9, seed2=12,seed3=15;

always

begin

add1={KaTeX parse error: Expected ‘EOF’, got ‘}’ at position 15: random(seed1) }̲%128; add2={random(seed2) }%128;
add_cin={$random (seed3) }/2;
#60;
end
initial clock=0;

always #15 clock=~clock;

add_pp myadd(add1,add2,add_cin,add_sum, add_cout,clock);

endmodule

module add_pp (a,b, cin, sum, cout,clock) ;

input [7:0]a,b;

input cin,clock;

output [7:0]sum;

output cout;

reg c1o;

wire c1;

always @ (posedge clock)
c1o<=c1;

assign {cout,sum[7:4]}=a[7:4]+b[7:4]+c1o;
assign {c1,sum[3:0]}=a[3:0]+b[3:0]+cin;

endmodule

高级数字设计P183例题6.27：
module Seq_Rec_3_1s_Mealy(output D_out, input D_in, En, clk, reset);

parameter S_idle=2’d0,
S_0= 2’d1,

          S_1= 2'd2,

          S_2= 2'd3,

          S_3= 2'd4;

reg [1:0] state, next_state;
reg D_out_reg;
always@(negedge clk)
if (reset1) D_out_reg<=0;
else D_out_reg<=((resetS_2)&&(D_in==1));

always @ (negedge clk)

if (reset==1) state<= S_idle; else state <= next_state;

always @ (state, En, D_in)

begin

next_state=S_idle;

case(state)

S_idle: if ((En1)&&(D_in 1)) next_state=S_1;

                else if((En== 1)&&(D_in== 0))  next_state=S_0;
                else                          next_state= S_idle;

S_0: if(D_in==0) next_state= S_0;

                    else if(D_in== 1)             next_state=S_1;
                    else                        next_state=S_idle;

S_1: if(D_in== 0) next_state=S_0;

                  else if(D_in== 1)           next_state=S_2;

                 else                      next_state = S_idle;

S_2: if(D_in==0) next_state=S_0;

                    else if(D_in==1)                   next_state=S_2;

                       else                             next_state= S_idle;

default: next_state= S_idle;

endcase

end

assign D_out= ((stateS_2)&&(D_in1 ));
endmodule

module Seq_Rec_3_1s_Moore(output D_out, input D_in, En, clk, reset);

parameter S_idle = 3’d0,

          S_0= 3'd1,

          S_1=3'd2,

          S_2= 3'd3,

          S_3=3'd4;

reg [2:0] state, next_state;
reg D_out_reg;
always@(negedge clk)
if(reset1)D_out_reg<=0;
else D_out_reg<=((stateS_2)&&(next_stateS_2)&&(D_in1));

always @ (negedge clk)

if(reset== 1) state <=S_idle; else state <= next_state;

always @ (state, En, D_in)

begin

case (state)

S_idle: if((En== 1)&&(D_in== 1)) next_state=S_1;

else

if((En== 1)&&(D_in== 0)) next_state=S_0;

else next_state= S_idle;

S_0: if(D_in== 0) next_state=S_0; else

    if(D_in== 1) next_state=S_1;

                                   else 
                                  next_state=S_idle;

   S_1: if(D_in== 0)  next_state=S_0; else

       if(D_in== 1) next_state=S_2; else 
                             next_state= S_idle;

   S_2,S_3: if(D_in==0) next_state=S_0; else

if(D_in== 1) next_state=S_3;

else next_state= S_idle;

default: next_state= S_idle;

endcase
end

assign D_out= (state==S_3);

endmodule

8.软件下载网站：
1.复制这段内容后打开百度网盘App，操作更方便哦。 链接:https://pan.baidu.com/s/1ZT0ovNAAZ_j3jTGzVCYfbQ
提取码：5jf2
2.复制这段内容后打开百度网盘App，操作更方便哦。 链接:https://pan.baidu.com/s/1bkD2-5Gwl1HB6y9hkUF14A 提取码:540y