学习及反思2：verilog达芬奇VGA彩条显示实验

使用到的：正点原子达芬奇开发板，800*480正点原子液晶屏模块，b站小梅哥视频

通过B站小梅哥TFT学习视频，进行部分理解修改使用正点原子显示。

反思：正点原子使用的代码中是采用DE模式，DE模式中DE为1，将行场同步信号赋予1。而小梅哥是将行场脉冲信号赋予给行场同步信号即VGA_HS VGA_VS。经过理解，小梅哥代码中的VGA_BLK信号就是DE信号，当像素进行看的见的有效区域（800*480）中，将VGA_BLK拉高，此时即DE，DE则为1；而行场同步信号在有效区域前脉冲区域是为0的，当VGA_BLK拉高时，VGA_HS和VGA_VS都已经为1了，即处于DE模式中。

• 顶层代码：

//800*480
module VGA_CTRL_test(
    Clk,    //系统时钟50MHZ
    Reset_n,
    VGA_RGB,//VGA数据输出
    VGA_HS, //VGA行同步信号
    VGA_VS, //VGA场同步信号
    VGA_BLK, //VGA 场消隐信号 该信号为DE信号
	VGA_RST,  //VGA复位信号
    VGA_CLK, //VGA时钟信号
    TFT_BL  //背光
);

    input Clk;
    input Reset_n;
    output [23:0]VGA_RGB;
    output VGA_HS;
    output VGA_VS;
    output VGA_BLK;     //VGA 场消隐信号
    output VGA_CLK; 
    output TFT_BL;
    output VGA_RST;
	
    assign TFT_BL = 1;
    assign VGA_RST = 1;
	
    reg [23:0]disp_data;
    wire [11:0]hcount;
    wire [11:0]vcount;
    wire Clk33M; 
	wire Data_Req;
	
	
	assign VGA_CLK= Clk33M;
	
	vga_pll vga_pll(
        .clk_out1(Clk33M),
        .clk_in1(Clk)
    );      

    VGA_CTRL VGA_CTRL(
        .Clk(Clk33M),    //LCD输入时钟33MHZ
        .Reset_n(Reset_n),
        .Data(disp_data),    //待显示数据
		.Data_Req(Data_Req),
        .hcount(hcount),        //VGA行扫描计数器
        .vcount(vcount),        //VGA场扫描计数器
        .VGA_RGB(VGA_RGB),  //VGA数据输出
        .VGA_HS(VGA_HS),        //VGA行同步信号
        .VGA_VS(VGA_VS),        //VGA场同步信号
        .VGA_BLK(VGA_BLK)      //VGA 场消隐信号
    );
        
//定义颜色编码
localparam 
    BLACK       = 24'h000000, //黑色
    BLUE        = 24'h0000FF, //蓝色
    RED     = 24'hFF0000, //红色
    PURPPLE = 24'hFF00FF, //紫色
    GREEN       = 24'h00FF00, //绿色
    CYAN        = 24'h00FFFF, //青色
    YELLOW  = 24'hFFFF00, //黄色
    WHITE       = 24'hFFFFFF; //白色
    
//定义每个像素块的默认显示颜色值
localparam 
    R0_C0 = BLACK,  //第0行0列像素块
    R0_C1 = BLUE,   //第0行1列像素块
    R1_C0 = RED,    //第1行0列像素块
    R1_C1 = PURPPLE,//第1行1列像素块
    R2_C0 = GREEN,  //第2行0列像素块
    R2_C1 = CYAN,   //第2行1列像素块
    R3_C0 = YELLOW, //第3行0列像素块
    R3_C1 = WHITE;  //第3行1列像素块
//行像素 即480
    wire R0_act = vcount >= 0 && vcount < 120;  //正在扫描第0行
    wire R1_act = vcount >= 120 && vcount < 240;//正在扫描第1行
    wire R2_act = vcount >= 240 && vcount < 360;//正在扫描第2行
    wire R3_act = vcount >= 360 && vcount < 480;//正在扫描第3行
//场像素 即800
    wire C0_act = hcount >= 0 && hcount < 400; //正在扫描第0列
    wire C1_act = hcount >= 400 && hcount < 800;//正在扫描第1列 
    
    wire R0_C0_act=R0_act & C0_act;//第0行0列像素块处于被扫描中标志信号
    wire R0_C1_act=R0_act & C1_act;//第0行1列像素块处于被扫描中标志信号
    wire R1_C0_act=R1_act & C0_act;//第1行0列像素块处于被扫描中标志信号
    wire R1_C1_act=R1_act & C1_act;//第1行1列像素块处于被扫描中标志信号
    wire R2_C0_act=R2_act & C0_act;//第2行0列像素块处于被扫描中标志信号
    wire R2_C1_act=R2_act & C1_act;//第2行1列像素块处于被扫描中标志信号
    wire R3_C0_act=R3_act & C0_act;//第3行0列像素块处于被扫描中标志信号
    wire R3_C1_act=R3_act & C1_act;//第3行1列像素块处于被扫描中标志信号
    
    always@(*)
        case({R3_C1_act,R3_C0_act,R2_C1_act,R2_C0_act,
                R1_C1_act,R1_C0_act,R0_C1_act,R0_C0_act})
            8'b0000_0001:disp_data = R0_C0;
            8'b0000_0010:disp_data = R0_C1;
            8'b0000_0100:disp_data = R1_C0;
            8'b0000_1000:disp_data = R1_C1;
            8'b0001_0000:disp_data = R2_C0;
            8'b0010_0000:disp_data = R2_C1;
            8'b0100_0000:disp_data = R3_C0;
            8'b1000_0000:disp_data = R3_C1;
            default:disp_data = R0_C0;
        endcase
        
endmodule

• VGA控制器模块：

module VGA_CTRL(
    Clk,
    Reset_n,
    Data,
    Data_Req,
    hcount,
    vcount,
    VGA_HS,
    VGA_VS,
    VGA_BLK,
    VGA_RGB
);
    
    input Clk;
    input Reset_n;
    input [23:0]Data;
    output reg Data_Req;
    output reg [11:0]hcount; //当前扫描点的H坐标
    output reg [11:0]vcount; //当前扫描点的V坐标
    output reg VGA_HS;
    output reg VGA_VS; 
    output reg VGA_BLK;
    output reg [23:0]VGA_RGB;
 //行场同步各个时间节点
    `include "vga_parameter.v"
    localparam Hsync_End = `H_Total_Time;
    localparam HS_End = `H_Sync_Time;
    localparam Hdat_Begin = `H_Sync_Time + `H_Back_Porch + `H_Left_Border;
    localparam Hdat_End = `H_Sync_Time + `H_Left_Border + `H_Back_Porch + `H_Data_Time;
    localparam Vsync_End = `V_Total_Time;
    localparam VS_End = `V_Sync_Time;
    localparam Vdat_Begin =  `V_Sync_Time + `V_Back_Porch + `V_Top_Border;
    localparam Vdat_End = `V_Sync_Time + `V_Back_Porch + `V_Top_Border + `V_Data_Time;
//行扫描计数器    
    reg [11:0]hcnt;
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        hcnt <= 0;
    else if(hcnt >= Hsync_End -1)
        hcnt <= 0;
    else
        hcnt <= hcnt + 1'b1;
//行同步信号
    always@(posedge Clk)
        VGA_HS <= (hcnt < HS_End)?0:1;
//场扫描计数器 
    reg [11:0]vcnt;
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        vcnt <= 0;
    else if(hcnt == Hsync_End -1)begin
        if(vcnt >= Vsync_End -1)
            vcnt <= 0;
        else
            vcnt <= vcnt + 1'd1;
    end
    else
        vcnt <= vcnt;
//场同步信号
    always@(posedge Clk)
        VGA_VS  <= (vcnt < VS_End)?0:1;
//用于延时一个单位，使VGA_RGB和VGA_BLK对起 
    always@(posedge Clk)
       Data_Req <= ((hcnt >= Hdat_Begin - 1) && (hcnt < Hdat_End - 1) && (vcnt >= Vdat_Begin) && (vcnt < Vdat_End))?1:0;
    
    always@(posedge Clk)
       VGA_BLK <= Data_Req;     
            
    always@(posedge Clk)
        VGA_RGB <= Data_Req? Data:0;
        
    always@(posedge Clk)
       hcount <= Data_Req? hcnt - Hdat_Begin:0; 

    always@(posedge Clk)
       vcount <= Data_Req? vcnt - Vdat_Begin:0;          
        
endmodule

VGA控制器模块中的`include "vga_parameter.v"需加入一个各分辨率时间点的V文件。

• .v文件

//`define Resolution_480x272 1	//刷新率为60Hz时像素时钟为9MHz
//`define Resolution_640x480 1	//刷新率为60Hz时像素时钟为25.175MHz
`define Resolution_800x480 1	//刷新率为60Hz时像素时钟为33MHz
//`define Resolution_800x600 1	//刷新率为60Hz时像素时钟为40MHz
//`define Resolution_1024x768 1	//刷新率为60Hz时像素时钟为65MHz
//`define Resolution_1280x720 1	//刷新率为60Hz时像素时钟为74.25MHz
//`define Resolution_1920x1080 1	//刷新率为60Hz时像素时钟为148.5MHz

`ifdef Resolution_480x272    
    `define H_Right_Border 0
    `define H_Front_Porch 2
    `define H_Sync_Time 41
    `define H_Back_Porch 2
    `define H_Left_Border 0
    `define H_Data_Time 480
    `define H_Total_Time 525
    `define V_Bottom_Border 0
    `define V_Front_Porch 2
    `define V_Sync_Time 10
    `define V_Back_Porch 2
    `define V_Top_Border 0
    `define V_Data_Time 272
    `define V_Total_Time 286
    
`elsif Resolution_640x480
	`define H_Total_Time  12'd800
	`define H_Right_Border  12'd8
	`define H_Front_Porch  12'd8
	`define H_Sync_Time  12'd96
	`define H_Data_Time 12'd640
	`define H_Back_Porch  12'd40
	`define H_Left_Border  12'd8
	`define V_Total_Time  12'd525
	`define V_Bottom_Border  12'd8
	`define V_Front_Porch  12'd2
	`define V_Sync_Time  12'd2
	`define V_Data_Time 12'd480
	`define V_Back_Porch  12'd25
	`define V_Top_Border  12'd8
	
`elsif Resolution_800x480
	`define H_Total_Time 12'd1056
	`define H_Right_Border 12'd0
	`define H_Front_Porch 12'd40
	`define H_Sync_Time 12'd128
	`define H_Data_Time 12'd800
	`define H_Back_Porch 12'd88
	`define H_Left_Border 12'd0

	`define V_Total_Time 12'd525
	`define V_Bottom_Border 12'd8
	`define V_Front_Porch 12'd2
	`define V_Sync_Time 12'd2
	`define V_Data_Time 12'd480
	`define V_Back_Porch 12'd25
	`define V_Top_Border 12'd8

`elsif Resolution_800x600
	`define H_Total_Time 12'd1056
	`define H_Right_Border 12'd0
	`define H_Front_Porch 12'd40
	`define H_Sync_Time 12'd128
	`define H_Data_Time 12'd800
	`define H_Back_Porch 12'd88
	`define H_Left_Border 12'd0

	`define V_Total_Time 12'd628
	`define V_Bottom_Border 12'd0
	`define V_Front_Porch 12'd1
	`define V_Sync_Time 12'd4
	`define V_Data_Time 12'd600
	`define V_Back_Porch 12'd23
	`define V_Top_Border 12'd0

`elsif Resolution_1024x768
	`define H_Total_Time 12'd1344
	`define H_Right_Border 12'd0
	`define H_Front_Porch 12'd24
	`define H_Sync_Time 12'd136
	`define H_Data_Time 12'd1024
	`define H_Back_Porch 12'd160
	`define H_Left_Border 12'd0

	`define V_Total_Time 12'd806
	`define V_Bottom_Border 12'd0
	`define V_Front_Porch 12'd3
	`define V_Sync_Time 12'd6
	`define V_Data_Time 12'd768
	`define V_Back_Porch 12'd29
	`define V_Top_Border 12'd0

`elsif Resolution_1280x720
	`define H_Total_Time 12'd1650
	`define H_Right_Border 12'd0
	`define H_Front_Porch 12'd110
	`define H_Sync_Time 12'd40
	`define H_Data_Time 12'd1280
	`define H_Back_Porch 12'd220
	`define H_Left_Border 12'd0

	`define V_Total_Time 12'd750
	`define V_Bottom_Border 12'd0
	`define V_Front_Porch 12'd5
	`define V_Sync_Time 12'd5
	`define V_Data_Time 12'd720
	`define V_Back_Porch 12'd20
	`define V_Top_Border 12'd0
		
`elsif Resolution_1920x1080
	`define H_Total_Time 12'd2200
	`define H_Right_Border 12'd0
	`define H_Front_Porch 12'd88
	`define H_Sync_Time 12'd44
	`define H_Data_Time 12'd1920
	`define H_Back_Porch 12'd148
	`define H_Left_Border 12'd0

	`define V_Total_Time 12'd1125
	`define V_Bottom_Border 12'd0
	`define V_Front_Porch 12'd4
	`define V_Sync_Time 12'd5
	`define V_Data_Time 12'd1080
	`define V_Back_Porch 12'd36
	`define V_Top_Border 12'd0	
	
`endif

需要用到哪个分辨率的就将开头的注释去掉即使用，具体使用可以去看b站小梅哥FPGA。

• 约束引脚文件代码

set_property PACKAGE_PIN U2 [get_ports Reset_n]
set_property PACKAGE_PIN R4 [get_ports Clk]
set_property IOSTANDARD LVCMOS33 [get_ports Clk]
set_property IOSTANDARD LVCMOS33 [get_ports Reset_n]
set_property PACKAGE_PIN V7 [get_ports TFT_BL]
set_property IOSTANDARD LVCMOS33 [get_ports TFT_BL]
set_property PACKAGE_PIN AB7 [get_ports VGA_BLK]
set_property PACKAGE_PIN Y9 [get_ports VGA_CLK]
set_property PACKAGE_PIN V8 [get_ports VGA_HS]
set_property PACKAGE_PIN W7 [get_ports VGA_RST]
set_property PACKAGE_PIN U7 [get_ports VGA_VS]
set_property IOSTANDARD LVCMOS33 [get_ports VGA_BLK]
set_property IOSTANDARD LVCMOS33 [get_ports VGA_CLK]
set_property IOSTANDARD LVCMOS33 [get_ports VGA_HS]
set_property IOSTANDARD LVCMOS33 [get_ports VGA_RST]
set_property IOSTANDARD LVCMOS33 [get_ports VGA_VS]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[23]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[21]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[19]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[18]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[17]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RGB[0]}]
set_property PACKAGE_PIN R16 [get_ports {VGA_RGB[0]}]
set_property PACKAGE_PIN P15 [get_ports {VGA_RGB[1]}]
set_property PACKAGE_PIN R14 [get_ports {VGA_RGB[2]}]
set_property PACKAGE_PIN P14 [get_ports {VGA_RGB[3]}]
set_property PACKAGE_PIN N14 [get_ports {VGA_RGB[4]}]
set_property PACKAGE_PIN N13 [get_ports {VGA_RGB[5]}]
set_property PACKAGE_PIN V9 [get_ports {VGA_RGB[6]}]
set_property PACKAGE_PIN W9 [get_ports {VGA_RGB[7]}]
set_property PACKAGE_PIN U18 [get_ports {VGA_RGB[8]}]
set_property PACKAGE_PIN U17 [get_ports {VGA_RGB[9]}]
set_property PACKAGE_PIN V19 [get_ports {VGA_RGB[10]}]
set_property PACKAGE_PIN T18 [get_ports {VGA_RGB[11]}]
set_property PACKAGE_PIN V20 [get_ports {VGA_RGB[12]}]
set_property PACKAGE_PIN R18 [get_ports {VGA_RGB[13]}]
set_property PACKAGE_PIN N17 [get_ports {VGA_RGB[14]}]
set_property PACKAGE_PIN P17 [get_ports {VGA_RGB[15]}]
set_property PACKAGE_PIN AB18 [get_ports {VGA_RGB[16]}]
set_property PACKAGE_PIN AA18 [get_ports {VGA_RGB[17]}]
set_property PACKAGE_PIN Y19 [get_ports {VGA_RGB[18]}]
set_property PACKAGE_PIN Y18 [get_ports {VGA_RGB[19]}]
set_property PACKAGE_PIN W20 [get_ports {VGA_RGB[20]}]
set_property PACKAGE_PIN W17 [get_ports {VGA_RGB[21]}]
set_property PACKAGE_PIN V18 [get_ports {VGA_RGB[22]}]
set_property PACKAGE_PIN V17 [get_ports {VGA_RGB[23]}]

约束引脚代码仅对应正点原子达芬奇开发板以及上述代码中对应端口。

• 实物验证