期末实验三

一.实验目的
加强对行为级建模的掌握

二.实验内容
用verilog代码与Modelsim软件实现行为级建模

三.实验原理
按照视频上的内容，书写和运行代码，完成仿真

四.实验工具
Modelsim软件

五.实验过程截图



六.实验视频
【bandicam 2021-06-29 12-49-41-828-哔哩哔哩】https://b23.tv/LON9NJ

七.实验代码
module digital(TimerH, TimerL, over, Reset,Stop,clk);
output [6:0] TimerH;
output [6:0] TimerL;
output over;
input Reset;
input Stop;
input clk;
wire [1:0]H;
wire [3:0]L;
wire clk_1;
fenpin U0(.clk(clk),.clk_old(clk_1));
basketballtimer U1(over, H[1:0], L[3:0], Reset, Stop, clk_1);
CD4511 U2(TimerH[6:0], {2’b00,H[1:0]});
CD4511 U3(TimerL[6:0], L[3:0]);
endmodule
module fenpin(clk_old,clk);
output clk_old;
input clk;
reg [24:0] count;
reg clk_old;
always @ (posedge clk)
begin
if (count==25’b1_1001_0000_0000_0000_0000_0000)
begin
clk_old<=~clk_old;
count<=0;
end
else
count<=count+1;

end

endmodule

module basketballtimer(Over, TimerH, TimerL, Reset,Stop,clk_1);

output Over;

output [1 :0] TimerH;

output [3:0] TimerL;

input Reset;

input Stop;

input clk_1;

reg [4:0]Q;
assign Over =(Q == 5’d0);
assign TimerH=Q/10;

assign TimerL=Q%10;

always @ (posedge clk_1 or negedge Reset or negedge Stop)

begin

if (~Reset)

Q <=5’d23;

else

begin

if (~Stop)

Q<=Q;

else

begin

if (Q>5’d0)

Q <= Q-1 'b1;

else

Q <=Q;

end

end

end

endmodule

module CD4511(Y,A);

output reg[6:0]Y;

input [3:0]A;

always @ (*)

begin
case (A)

4’d0: Y<=7’b1000_000;
4’d1: Y<=7’b1111_001;
4’d2: Y<=7’b0100_100;
4’d3: Y<=7’b0110_000;
4’d4: Y<=7’b0011_001;
4’d5: Y<=7’b0010_010;
4’d6: Y<=7’b0000_010;
4’d7: Y<=7’b1111_000;
4’d8: Y<=7’b0000_000;
4’d9: Y<=7’b0010_000;

default: Y<=7’b1000_000;
endcase

end

endmodule