一、VGA原理
（一）VGA协议
VGA(Video Graphics Array)是IBM在1987年随PS/2机⼀起推出的⼀种视频，具有分辨率⾼、显⽰速率快、颜⾊丰富等优点，在彩 ⾊显⽰器领域得到了⼴泛的应⽤。不⽀持热插拔，不⽀持⾳频传输。对于⼀些嵌⼊式VGA显⽰系统，可以在不使⽤VGA显⽰卡和计算机的 情况下，实现VGA图像的显⽰和控制。VGA显⽰器具有成本低、结构简单、应⽤灵活的优点。
（二）VGA端口结构
VGA端口是视频输出端口，端口一共包含15个管脚，如下图
在通常使用的连接方法里面，15个管脚里面的5个是最重要的，他们包括3个基本红，绿，蓝三条基本色彩线和水平与垂直两条控制线。
（三）⾊彩原理
三基⾊是指通过其他颜⾊的混合⽆法得到的“基本 ⾊”由于⼈的⾁眼有感知红、绿、蓝三种不同颜⾊的锥体细胞，因此⾊彩空间通常可以由三种基本⾊来表达
二、VGA显示彩色条纹
- 顶层模块
//顶层文件
module vga_top(
input clk ,//时钟信号
input rst_n ,//复位信号
output wire hsync ,//
output wire vsync ,//
output wire sync ,
output wire [7:0] vga_r ,//三通道,红色
output wire [7:0] vga_g ,//三通道,绿色
output wire [7:0] vga_b ,//三通道,蓝色
output wire vga_blk ,
output wire vga_clk
);
wire [10:0] h_addr ;//数据有效显示区域行地址
wire [10:0] v_addr ;//数据有效显示区域场地址
wire [23:0] data_dis;
//例化
data_gen u_data_gen(
.clk (clk ) ,//时钟信号
.rst_n (rst_n ) ,//复位信号
.h_addr (h_addr ) ,//数据有效显示区域行地址
.v_addr (v_addr ) ,//数据有效显示区域场地址
.data_dis (data_dis) //需要显示的信号
);
//例化
vga_ctrl u_vga_ctrl(
.clk (clk ) ,//时钟信号
.rst_n (rst_n ) ,//复位信号
.data_dis (data_dis) ,//需要显示的信号
.h_addr (h_addr ) ,//数据有效显示区域行地址
.v_addr (v_addr ) ,//数据有效显示区域场地址
.hsync (hsync ) ,//
.vsync (vsync ) ,//
.sync (sync ) ,
.vga_r (vga_r ) ,//三通道,红色
.vga_g (vga_g ) ,//三通道,绿色
.vga_b (vga_b ) ,//三通道,蓝色
.vga_blk (vga_blk ) ,
.vga_clk (vga_clk ) //显示器显示时钟
);
endmodule
- 彩条模块
//数据生成
module data_gen(
input clk ,//时钟信号
input rst_n ,//复位信号
input [10:0] h_addr ,//数据有效显示区域行地址
input [10:0] v_addr ,//数据有效显示区域场地址
output reg [23:0] data_dis //需要显示的信号
);
//参数定义
parameter BLACK = 24'h000000,
RED = 24'hFF0000,
GREEN = 24'h00FF00,
BLUE = 24'h0000FF,
YELLOW = 24'hFFFF00,
SKY_BLUE = 24'h00FFFF,
PURPLE = 24'hFF00FF,
GRAY = 24'hC0C0C0,
WHITE = 24'hFFFFFF;
//赋值
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_dis <= BLACK;
end
else begin
case(h_addr)
0 : data_dis <= BLUE ;
80 : data_dis <= RED ;
160 : data_dis <= GREEN ;
240 : data_dis <= BLUE ;
320 : data_dis <= YELLOW ;
400 : data_dis <= SKY_BLUE ;
480 : data_dis <= PURPLE ;
560 : data_dis <= GRAY ;
default: data_dis <= data_dis ;
endcase
end
end
endmodule
- VGA显示模块
//VGA显示，实训讲解
`define vga_640_480
`include "vga_para.v"
module vga_ctrl(
input clk ,//时钟信号
input rst_n ,//复位信号
input [23:0] data_dis,//需要显示的信号
output reg [10:0] h_addr ,//数据有效显示区域行地址
output reg [10:0] v_addr ,//数据有效显示区域场地址
output reg hsync ,//行同步信号
output reg vsync ,//场同步信号
output sync ,
output reg [7:0] vga_r ,//三通道,红色
output reg [7:0] vga_g ,//三通道,绿色
output reg [7:0] vga_b ,//三通道,蓝色
output reg vga_blk ,//复合空白信号控制信号,VGA消隐信号显示数据时为1电产,其他时候为低电平
output vga_clk //显示器显示时钟
);
//参数定义
parameter H_SYNC_STA = 1 ;
parameter H_SYNC_STO = `H_Sync_Time ;
parameter H_Data_STA = `H_Sync_Time + `H_Back_Porch + `H_Left_Border;
parameter H_Data_STO = `H_Sync_Time + `H_Back_Porch + `H_Left_Border + `H_Data_Time;
parameter V_SYNC_STA = 1 ;
parameter V_SYNC_STO = `V_Sync_Time ;
parameter V_Data_STA = `V_Sync_Time + `V_Back_Porch + `V_Top_Border;
parameter V_Data_STO = `V_Sync_Time + `V_Back_Porch + `V_Top_Border + `V_Data_Time;
//信号定义
reg [11:0] cnt_h_addr;//行地址计数器
wire add_h_addr;
wire end_h_addr;
reg [11:0] cnt_v_addr;//场地址计数器
wire add_v_addr;
wire end_v_addr;
reg clk_25M ;
assign sync = 1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
clk_25M <= 1'b0;
end
else begin
clk_25M <= ~clk_25M;
end
end
assign vga_clk = clk_25M;
//cnt_h_addr
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_h_addr <= 12'd0;
end
else if(add_h_addr) begin
if(end_h_addr)begin
cnt_h_addr <= 12'd0;
end
else begin
cnt_h_addr = cnt_h_addr + 12'd1;
end
end
else begin
cnt_h_addr <= 12'd0;
end
end
assign add_h_addr = 1'b1;//开启条件
assign end_h_addr = add_h_addr && cnt_h_addr >= `H_Total_Time - 1;
//cnt_v_addr
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_v_addr <= 12'd0;
end
else if(add_v_addr) begin
if(end_v_addr)begin
cnt_v_addr <= 12'd0;
end
else begin
cnt_v_addr = cnt_v_addr + 12'd1;
end
end
else begin
cnt_v_addr = cnt_v_addr;
end
end
assign add_v_addr = end_h_addr;
assign end_v_addr = add_v_addr && cnt_v_addr >= `V_Total_Time - 1;
//行同步信号
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
hsync <= 1'b1;
end
else if(cnt_h_addr == H_SYNC_STA -1)begin
hsync <= 1'b0;
end
else if(cnt_h_addr == H_SYNC_STO - 1) begin
hsync <= 1'b1;
end
else begin
hsync <= hsync ;
end
end
//场同步信号
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vsync <= 1'b1;
end
else if(cnt_v_addr == V_SYNC_STA -1)begin
vsync <= 1'b0;
end
else if(cnt_v_addr == V_SYNC_STO - 1) begin
vsync <= 1'b1;
end
else begin
vsync <= vsync ;
end
end
//数据有效显示区域定义
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
h_addr <= 11'd0;
end
else if ((cnt_h_addr >= H_Data_STA - 1 )&&(cnt_h_addr <= H_Data_STO -1)) begin
h_addr <= cnt_h_addr - H_Data_STA -1 ;
end
else begin
h_addr <= 11'd0;
end
end
//场地址有效显示区域定义
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
v_addr <= 11'd0;
end
else if ((cnt_v_addr >= V_Data_STA - 1 )&& (cnt_v_addr <= V_Data_STO -1)) begin
v_addr <= cnt_v_addr - V_Data_STA -1 ;
end
else begin
v_addr <= 11'd0;
end
end
//显示数据
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vga_r <= 8'd0;
vga_b <= 8'd0;
vga_g <= 8'd0;
vga_blk <= 1'b0;
end
else if((cnt_h_addr >= H_Data_STA - 1 )&&(cnt_h_addr <= H_Data_STO -1)
&& (cnt_v_addr >= V_Data_STA - 1 )&& (cnt_v_addr <= V_Data_STO -1))begin
vga_r <= data_dis[23:16];//data_dis[23-:8]
vga_g <= data_dis[15:8] ;//data_dis[15-:8]
vga_b <= data_dis[7:0] ;//data_dis[7- :8]
vga_blk <= 1'b1;
end
else begin
vga_r <= 8'd0;
vga_b <= 8'd0;
vga_g <= 8'd0;
vga_blk <= 1'b0;
end
end
endmodule
- 参数模块
`define vga_640_480
`define vga_1920_1080
`define vga_1024_768
`ifdef vga_640_480 //执行操作B
`define H_Right_Border 8 //行同步右沿信号
`define H_Front_Porch 8 //行同步前沿信号周期长
`define H_Sync_Time 96 //行同步信号周期长
`define H_Back_Porch 40 //行同步后沿信号周期长
`define H_Left_Border 4 //行同步左沿信号
`define H_Data_Time 640 //行显示周期长
`define H_Total_Time 800
`define V_Bottom_Border 8 //场同步底沿信号
`define V_Front_Porch 2 //场同步前沿信号周期长
`define V_Sync_Time 2 //场同步信号周期长
`define V_Back_Porch 25 //场同步后沿信号周期长
`define V_Top_Border 8 //场同步顶沿信号
`define V_Data_Time 480 //场显示周期长
`define V_Total_Time 525
`elsif vga_1920_1080 //执行操作B
`define H_Right_Border 0
`define H_Front_Porch 88
`define H_Sync_Time 44
`define H_Back_Porch 148
`define H_Left_Border 0
`define H_Data_Time 1920
`define H_Total_Time 2200
`define V_Bottom_Border 0
`define V_Front_Porch 4
`define V_Sync_Time 5
`define V_Back_Porch 36
`define V_Top_Border 0
`define V_Data_Time 1080
`define V_Total_Time 1125
`elsif vga_1024_768
`define H_Right_Border 0
`define H_Front_Porch 24
`define H_Sync_Time 136
`define H_Back_Porch 160
`define H_Left_Border 0
`define H_Data_Time 1024
`define H_Total_Time 1344
`define V_Bottom_Borde 0
`define V_Front_Porch 3
`define V_Sync_Time 6
`define V_Back_Porch 29
`define V_Top_Border 0
`define V_Data_Time 768
`define V_Total_Time 806
`else //可以没有
`endif
结果显示：
三、VGA显示字符
代码如下：
module VGA_test(
OSC_50, //原CLK2_50时钟信号
VGA_CLK, //VGA自时钟
VGA_HS, //行同步信号
VGA_VS, //场同步信号
VGA_BLANK, //复合空白信号控制信号 当BLANK为低电平时模拟视频输出消隐电平，此时从R9~R0,G9~G0,B9~B0输入的所有数据被忽略
VGA_SYNC, //符合同步控制信号 行时序和场时序都要产生同步脉冲
VGA_R, //VGA绿色
VGA_B, //VGA蓝色
VGA_G); //VGA绿色
input OSC_50; //外部时钟信号CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; //行同步前沿信号周期长
parameter H_SYNC = 96; //行同步信号周期长
parameter H_BACK = 48; //行同步后沿信号周期长
parameter H_ACT = 640; //行显示周期长
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; //行空白信号总周期长
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; //行总周期长耗时
parameter V_FRONT = 11; //场同步前沿信号周期长
parameter V_SYNC = 2; //场同步信号周期长
parameter V_BACK = 31; //场同步后沿信号周期长
parameter V_ACT = 480; //场显示周期长
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; //场空白信号总周期长
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; //场总周期长耗时
reg [10:0] H_Cont; //行周期计数器
reg [10:0] V_Cont; //场周期计数器
wire [7:0] VGA_R; //VGA红色控制线
wire [7:0] VGA_G; //VGA绿色控制线
wire [7:0] VGA_B; //VGA蓝色控制线
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; //当前行第几个像素点
reg [10:0] Y; //当前场第几行
reg CLK_25;
always@(posedge OSC_50)
begin
CLK_25=~CLK_25; //时钟
end
assign VGA_SYNC = 1'b0; //同步信号低电平
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); //当行计数器小于行空白总长或场计数器小于场空白总长时，空白信号低电平
assign VGA_CLK = ~CLK_to_DAC; //VGA时钟等于CLK_25取反
assign CLK_to_DAC = CLK_25;
always@(posedge CLK_to_DAC)
begin
if(H_Cont<H_TOTAL) //如果行计数器小于行总时长
H_Cont<=H_Cont+1'b1; //行计数器+1
else H_Cont<=0; //否则行计数器清零
if(H_Cont==H_FRONT-1) //如果行计数器等于行前沿空白时间-1
VGA_HS<=1'b0; //行同步信号置0
if(H_Cont==H_FRONT+H_SYNC-1) //如果行计数器等于行前沿+行同步-1
VGA_HS<=1'b1; //行同步信号置1
if(H_Cont>=H_BLANK) //如果行计数器大于等于行空白总时长
X<=H_Cont-H_BLANK; //X等于行计数器-行空白总时长 （X为当前行第几个像素点）
else X<=0; //否则X为0
end
always@(posedge VGA_HS)
begin
if(V_Cont<V_TOTAL) //如果场计数器小于行总时长
V_Cont<=V_Cont+1'b1; //场计数器+1
else V_Cont<=0; //否则场计数器清零
if(V_Cont==V_FRONT-1) //如果场计数器等于场前沿空白时间-1
VGA_VS<=1'b0; //场同步信号置0
if(V_Cont==V_FRONT+V_SYNC-1) //如果场计数器等于行前沿+场同步-1
VGA_VS<=1'b1; //场同步信号置1
if(V_Cont>=V_BLANK) //如果场计数器大于等于场空白总时长
Y<=V_Cont-V_BLANK; //Y等于场计数器-场空白总时长 （Y为当前场第几行）
else Y<=0; //否则Y为0
end
reg valid_yr;
always@(posedge CLK_to_DAC)
if(V_Cont == 10'd32) //场计数器=32时
valid_yr<=1'b1; //行输入激活
else if(V_Cont==10'd512) //场计数器=512时
valid_yr<=1'b0; //行输入冻结
wire valid_y=valid_yr; //连线
reg valid_r;
always@(posedge CLK_to_DAC)
if((H_Cont == 10'd32)&&valid_y) //行计数器=32时
valid_r<=1'b1; //像素输入激活
else if((H_Cont==10'd512)&&valid_y) //行计数器=512时
valid_r<=1'b0; //像素输入冻结
wire valid = valid_r; //连线
wire[10:0] x_dis; //像素显示控制信号
wire[10:0] y_dis; //行显示控制信号
assign x_dis=X; //连线X
assign y_dis=Y; //连线Y
parameter //点阵字模：每一行char_lineXX是显示的一行，共272列
char_line00=272'h00000000000000000000000000000000000000000000000000000000000000000000, //第1行
char_line01=272'h00000000000000000000000000000000000000000000000000000000000000000000, //第2行
char_line02=272'h00000000000000000000000000000000, //第3行
char_line03=272'h00000000000000000000000000000000, //第4行
char_line04=272'h00000000000000000000000000000000, //第5行
char_line05=272'h7E7EFE00183C0838187E183818083C3C, //第6行
char_line06=272'h84849200244238442442244424384242, //第7行
char_line08=272'h04041000400208424204424242080202, //第9行
char_line07=272'h08081000404208424204424242084242, //第8行
char_line09=272'h080810005C0408424208424242080404, //第10行
char_line0a=272'h1010107E621808464208424642081818, //第11行
char_line0b=272'h202010004204083A4210423A42080404, //第12行
char_line0c=272'h20201000420208024210420242080202, //第13行
char_line0d=272'h42421000424208024210420242084242, //第14行
char_line0e=272'h42421000224208242410242424084242, //第15行
char_line0f=272'hFCFC38001C3C3E1818101818183E3C3C, //第16行
char_line10=272'h00000000000000000000000000000000, //第17行
char_line11=272'h00000000000000000000000000000000, //第18行
reg[8:0] char_bit;
always@(posedge CLK_to_DAC)
if(X==10'd144)char_bit<=9'd272; //当显示到144像素时准备开始输出图像数据
else if(X>10'd144&&X<10'd416) //左边距屏幕144像素到416像素时 416=144+272（图像宽度）
char_bit<=char_bit-1'b1; //倒着输出图像信息
reg[29:0] vga_rgb; //定义颜色缓存
always@(posedge CLK_to_DAC)
if(X>10'd144&&X<10'd416) //X控制图像的横向显示边界：左边距屏幕左边144像素 右边界距屏幕左边界416像素
begin case(Y) //Y控制图像的纵向显示边界：从距离屏幕顶部160像素开始显示第一行数据
10'd160:
if(char_line00[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000; //如果该行有数据 则颜色为红色
else vga_rgb<=30'b0000000000_0000000000_0000000000; //否则为黑色
10'd162:
if(char_line01[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd163:
if(char_line02[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd164:
if(char_line03[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd165:
if(char_line04[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd166:
if(char_line05[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd167:
if(char_line06[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd168:
if(char_line07[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd169:
if(char_line08[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd170:
if(char_line09[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd171:
if(char_line0a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd172:
if(char_line0b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd173:
if(char_line0c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd174:
if(char_line0d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd175:
if(char_line0e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd176:
if(char_line0f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd177:
if(char_line10[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd178:
if(char_line11[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd179:
if(char_line12[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd180:
if(char_line13[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd181:
if(char_line14[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd182:
if(char_line15[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd183:
if(char_line16[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd184:
if(char_line17[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd185:
if(char_line18[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd186:
if(char_line19[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd187:
if(char_line1a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd188:
if(char_line1b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd189:
if(char_line1c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd190:
if(char_line1d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd191:
if(char_line1e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd192:
if(char_line1f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
default:vga_rgb<=30'h0000000000; //默认颜色黑色
endcase
end
else vga_rgb<=30'h000000000; //否则黑色
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
结果显示：
参考
https://blog.csdn.net/cchulu/article/details/73876978
https://blog.csdn.net/weixin_56102526/article/details/124964347
https://blog.csdn.net/cchulu/article/details/73876978
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